[Intel-gfx] [PATCH] drm/i915: Reserving some Multi-thread forcewake bits.

[Rodrigo Vivi]

Bit 0: Currently bit used by i915. Ideally only i915 touches it
       in a Linux stack.

Bits 1 and 2: A while ago we were using Bit 1 for i915 and bit 2
       	      for the user space, until commit 7130630323c5 ("drm/i915:
	      Use fallback forcewake if primary ack missing") changed it
	      to bit 1.
	      Now we have a situation where PCODE is also using this bit-1
	      in one case, while it should actually be using the Bit-3.
	      So, let's redirect users back to bit-2 and mark this 1 as
	      reserved.

Bit 3: Let's reserve for PCODE.

Bit 4: Let's reserve for PSMI.

Cc: Tilak Tangudu <tilak.tangudu at intel.com>
Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 0a5c2648aaf0..15ceaaace4d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1399,8 +1399,11 @@
 #define FORCEWAKE_MT_ACK			_MMIO(0x130040)
 #define FORCEWAKE_ACK_HSW			_MMIO(0x130044)
 #define FORCEWAKE_ACK_GT_GEN9			_MMIO(0x130044)
-#define   FORCEWAKE_KERNEL			BIT(0)
-#define   FORCEWAKE_USER			BIT(1)
+#define   FORCEWAKE_KERNEL			BIT(0) /* For i915 use only */
+#define   FORCEWAKE_RSVD			BIT(1)
+#define   FORCEWAKE_USER			BIT(2)
+#define   FORCEWAKE_PCODE			BIT(3)
+#define   FORCEWAKE_PSMI			BIT(4)
 #define   FORCEWAKE_KERNEL_FALLBACK		BIT(15)
 #define FORCEWAKE_ACK				_MMIO(0x130090)
 #define VLV_GTLC_WAKE_CTRL			_MMIO(0x130090)
-- 
2.34.1