[Intel-gfx] [PATCH 2/2] drm/i915/display: Add workaround 22014263786

[Matt Roper]

On Tue, Apr 19, 2022 at 07:44:54AM -0700, José Roberto de Souza wrote:
> This workaround fixes screen flickers with FBC.
> 
> BSpec: 33450
> BSpec: 52890
> BSpec: 54369
> BSpec: 66624
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++++
>  drivers/gpu/drm/i915/i915_reg.h          | 1 +
>  2 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 670835318a1f1..b7bdb0739744a 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -811,6 +811,14 @@ static void intel_fbc_program_cfb(struct intel_fbc *fbc)
>  	fbc->funcs->program_cfb(fbc);
>  }
>  
> +static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
> +{
> +	/* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,dg2,adlp */
> +	if (DISPLAY_VER(fbc->i915) >= 11)
> +		intel_de_rmw(fbc->i915, ILK_DPFC_CHICKEN(fbc->id), 0,
> +			     DPFC_CHICKEN_FORCE_SLB_INVALIDATION);
> +}
> +
>  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>  {
>  	struct drm_i915_private *i915 = fbc->i915;
> @@ -1462,6 +1470,7 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
>  
>  	intel_fbc_update_state(state, crtc, plane);
>  
> +	intel_fbc_program_workarounds(fbc);
>  	intel_fbc_program_cfb(fbc);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fef71b242706a..0ec7123197fcb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1400,6 +1400,7 @@
>  #define   DPFC_HT_MODIFY			REG_BIT(31) /* pre-ivb */
>  #define   DPFC_NUKE_ON_ANY_MODIFICATION		REG_BIT(23) /* bdw+ */
>  #define   DPFC_CHICKEN_COMP_DUMMY_PIXEL		REG_BIT(14) /* glk+ */
> +#define   DPFC_CHICKEN_FORCE_SLB_INVALIDATION	REG_BIT(13) /* icl+ */
>  #define   DPFC_DISABLE_DUMMY0			REG_BIT(8) /* ivb+ */
>  
>  #define GLK_FBC_STRIDE(fbc_id)	_MMIO_PIPE((fbc_id), 0x43228, 0x43268)
> -- 
> 2.35.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795