[Intel-gfx] [PATCH 1/2] drm/i915/gt: Add dedicated function for non-ctx register tuning settings

[Lucas De Marchi]

On Fri, Aug 12, 2022 at 01:22:39PM -0700, Matt Roper wrote:
>The bspec performance tuning section gives recommended settings that the
>driver should program for various MMIO registers.  Although these
>settings aren't "workarounds" we use the workaround infrastructure to do
>this programming to make sure it is handled at the appropriate places
>and doesn't conflict with any real workarounds.
>
>Since more of these are starting to show up on recent platforms, it's a
>good time to create a dedicated function to hold them so that there's
>less ambiguity about how/where to implement new ones.
>
>Cc: Lucas De Marchi <lucas.demarchi at intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 42 ++++++++++++++-------
> 1 file changed, 28 insertions(+), 14 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index 59cf28baa472..a68d279b01f0 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -2102,13 +2102,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> 		/* Wa_1509235366:dg2 */
> 		wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS |
> 			    GLOBAL_INVALIDATION_MODE);
>-
>-		/*
>-		 * The following are not actually "workarounds" but rather
>-		 * recommended tuning settings documented in the bspec's
>-		 * performance guide section.
>-		 */
>-		wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> 	}
>
> 	if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
>@@ -2676,6 +2669,32 @@ ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> 	}
> }
>
>+/*
>+ * The bspec performance guide has recommended MMIO tuning settings.  These
>+ * aren't truly "workarounds" but we want to program them with the same
>+ * workaround infrastructure to ensure that they're automatically added to
>+ * the GuC save/restore lists, re-applied at the right times, and checked for
>+ * any conflicting programming requested by real workarounds.
>+ *
>+ * Programming settings should be added here only if their registers are not
>+ * part of an engine's register state context.  If a register is part of a
>+ * context, then any tuning settings should be programmed in an appropriate
>+ * function invoked by __intel_engine_init_ctx_wa().
>+ */
>+static void
>+add_render_compute_tuning_settings(struct drm_i915_private *i915,
>+				   struct i915_wa_list *wal)
>+{
>+	if (IS_PONTEVECCHIO(i915)) {
>+		wa_write(wal, XEHPC_L3SCRUB,
>+			 SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
>+	}
>+
>+	if (IS_DG2(i915)) {
>+		wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
>+	}
>+}
>+
> /*
>  * The workarounds in this function apply to shared registers in
>  * the general render reset domain that aren't tied to a
>@@ -2690,14 +2709,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> {
> 	struct drm_i915_private *i915 = engine->i915;
>
>-	if (IS_PONTEVECCHIO(i915)) {
>-		/*
>-		 * The following is not actually a "workaround" but rather
>-		 * a recommended tuning setting documented in the bspec's
>-		 * performance guide section.
>-		 */
>-		wa_write(wal, XEHPC_L3SCRUB, SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
>+	add_render_compute_tuning_settings(i915, wal);
>
>+	if (IS_PONTEVECCHIO(i915)) {
> 		/* Wa_16016694945 */
> 		wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
> 	}
>-- 
>2.37.1
>