[Intel-gfx] [PATCH v2 05/21] drm/i915/mtl: Define engine context layouts

[Balasubramani Vivekanandan]

On 18.08.2022 16:41, Radhakrishna Sripada wrote:
> From: Matt Roper <matthew.d.roper at intel.com>
> 
> The part of the media and blitter engine contexts that we care about for
> setting up an initial state are the same on MTL as they were on DG2
> (and PVC), so we need to update the driver conditions to re-use the DG2
> context table.
> 
> For render/compute engines, the part of the context images are nearly
> the same, although the layout had a very slight change --- one POSH
> register was removed and the placement of some LRI/noops adjusted
> slightly to compensate.
> 
> Bspec: 46261, 46260, 45585
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c | 47 ++++++++++++++++++++++++++++-
>  1 file changed, 46 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index eec73c66406c..d3833cbaabcb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -606,6 +606,49 @@ static const u8 dg2_rcs_offsets[] = {
>  	END
>  };
>  
> +static const u8 mtl_rcs_offsets[] = {
> +       NOP(1),
> +       LRI(15, POSTED),
> +       REG16(0x244),
> +       REG(0x034),
> +       REG(0x030),
> +       REG(0x038),
> +       REG(0x03c),
> +       REG(0x168),
> +       REG(0x140),
> +       REG(0x110),
> +       REG(0x1c0),
> +       REG(0x1c4),
> +       REG(0x1c8),
> +       REG(0x180),
> +       REG16(0x2b4),

Inspecting Bspecs 46261 and 46260 indicates the following 2 registers
are replaced by NOP for MTL. Can you check?
> +       REG(0x120),
> +       REG(0x124),

> +
> +       NOP(1),
> +       LRI(9, POSTED),
> +       REG16(0x3a8),
> +       REG16(0x28c),
> +       REG16(0x288),
> +       REG16(0x284),
> +       REG16(0x280),
> +       REG16(0x27c),
> +       REG16(0x278),
> +       REG16(0x274),
> +       REG16(0x270),
> +
> +       NOP(2),
> +       LRI(2, POSTED),
> +       REG16(0x5a8),
> +       REG16(0x5ac),
> +
> +       NOP(6),
> +       LRI(1, 0),
> +       REG(0x0c8),
> +
> +       END
> +};
> +
>  #undef END
>  #undef REG16
>  #undef REG
> @@ -624,7 +667,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
>  		   !intel_engine_has_relative_mmio(engine));
>  
>  	if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
> -		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> +		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
> +			return mtl_rcs_offsets;
> +		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
>  			return dg2_rcs_offsets;
>  		else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
>  			return xehp_rcs_offsets;

Similarly from Bpsec 45582, the same 2 registers indicated above is
replaced by NOP even in Copy and Blitter engine contexts in MTL compared
to DG2. So we have to create a new structure for MTL for Copy and Media
engine contexts.

Regards,
Bala
> -- 
> 2.25.1
>