[Intel-gfx] [PATCH v5 04/10] drm/i915/guc: Add Gen9 registers for GuC error state capture.
Umesh Nerlige Ramappa
umesh.nerlige.ramappa at intel.com
Mon Feb 7 19:14:40 UTC 2022
lgtm,
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa at intel.com>
Umesh
On Wed, Jan 26, 2022 at 02:48:16AM -0800, Alan Previn wrote:
>Abstract out a Gen9 register list as the default for all other
>platforms we don't yet formally support GuC submission on.
>
>Signed-off-by: Alan Previn <alan.previn.teres.alexis at intel.com>
>---
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 74 +++++++++++++++----
> 1 file changed, 58 insertions(+), 16 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
>index 19719daffed4..70d2ee841289 100644
>--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
>+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
>@@ -19,15 +19,24 @@
> * NOTE: For engine-registers, GuC only needs the register offsets
> * from the engine-mmio-base
> */
>+#define COMMON_BASE_GLOBAL() \
>+ {FORCEWAKE_MT, 0, 0, "FORCEWAKE_MT"}
>+
>+#define COMMON_GEN9BASE_GLOBAL() \
>+ {GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0"}, \
>+ {GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1"}, \
>+ {ERROR_GEN6, 0, 0, "ERROR_GEN6"}, \
>+ {DONE_REG, 0, 0, "DONE_REG"}, \
>+ {HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN"}
>+
> #define COMMON_GEN12BASE_GLOBAL() \
> {GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0"}, \
> {GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1"}, \
>- {FORCEWAKE_MT, 0, 0, "FORCEWAKE_MT"}, \
> {GEN12_AUX_ERR_DBG, 0, 0, "GEN12_AUX_ERR_DBG"}, \
> {GEN12_GAM_DONE, 0, 0, "GEN12_GAM_DONE"}, \
> {GEN12_RING_FAULT_REG, 0, 0, "GEN12_RING_FAULT_REG"}
>
>-#define COMMON_GEN12BASE_ENGINE_INSTANCE() \
>+#define COMMON_BASE_ENGINE_INSTANCE() \
> {RING_PSMI_CTL(0), 0, 0, "RING_PSMI_CTL"}, \
> {RING_ESR(0), 0, 0, "RING_ESR"}, \
> {RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LOW32"}, \
>@@ -61,11 +70,13 @@
> {GEN8_RING_PDP_LDW(0, 3), 0, 0, "GEN8_RING_PDP3_LDW"}, \
> {GEN8_RING_PDP_UDW(0, 3), 0, 0, "GEN8_RING_PDP3_UDW"}
>
>-#define COMMON_GEN12BASE_HAS_EU() \
>+#define COMMON_BASE_HAS_EU() \
> {EIR, 0, 0, "EIR"}
>
>+#define COMMON_BASE_RENDER() \
>+ {GEN7_SC_INSTDONE, 0, 0, "GEN7_SC_INSTDONE"}
>+
> #define COMMON_GEN12BASE_RENDER() \
>- {GEN7_SC_INSTDONE, 0, 0, "GEN7_SC_INSTDONE"}, \
> {GEN12_SC_INSTDONE_EXTRA, 0, 0, "GEN12_SC_INSTDONE_EXTRA"}, \
> {GEN12_SC_INSTDONE_EXTRA2, 0, 0, "GEN12_SC_INSTDONE_EXTRA2"}
>
>@@ -77,23 +88,26 @@
>
> /* XE_LPD - Global */
> static struct __guc_mmio_reg_descr xe_lpd_global_regs[] = {
>+ COMMON_BASE_GLOBAL(),
>+ COMMON_GEN9BASE_GLOBAL(),
> COMMON_GEN12BASE_GLOBAL(),
> };
>
> /* XE_LPD - Render / Compute Per-Class */
> static struct __guc_mmio_reg_descr xe_lpd_rc_class_regs[] = {
>- COMMON_GEN12BASE_HAS_EU(),
>+ COMMON_BASE_HAS_EU(),
>+ COMMON_BASE_RENDER(),
> COMMON_GEN12BASE_RENDER(),
> };
>
>-/* XE_LPD - Render / Compute Per-Engine-Instance */
>+/* GEN9/XE_LPD - Render / Compute Per-Engine-Instance */
> static struct __guc_mmio_reg_descr xe_lpd_rc_inst_regs[] = {
>- COMMON_GEN12BASE_ENGINE_INSTANCE(),
>+ COMMON_BASE_ENGINE_INSTANCE(),
> };
>
>-/* XE_LPD - Media Decode/Encode Per-Engine-Instance */
>+/* GEN9/XE_LPD - Media Decode/Encode Per-Engine-Instance */
> static struct __guc_mmio_reg_descr xe_lpd_vd_inst_regs[] = {
>- COMMON_GEN12BASE_ENGINE_INSTANCE(),
>+ COMMON_BASE_ENGINE_INSTANCE(),
> };
>
> /* XE_LPD - Video Enhancement Per-Class */
>@@ -101,18 +115,33 @@ static struct __guc_mmio_reg_descr xe_lpd_vec_class_regs[] = {
> COMMON_GEN12BASE_VEC(),
> };
>
>-/* XE_LPD - Video Enhancement Per-Engine-Instance */
>+/* GEN9/XE_LPD - Video Enhancement Per-Engine-Instance */
> static struct __guc_mmio_reg_descr xe_lpd_vec_inst_regs[] = {
>- COMMON_GEN12BASE_ENGINE_INSTANCE(),
>+ COMMON_BASE_ENGINE_INSTANCE(),
> };
>
>-/* XE_LPD - Blitter Per-Engine-Instance */
>+/* GEN9/XE_LPD - Blitter Per-Engine-Instance */
> static struct __guc_mmio_reg_descr xe_lpd_blt_inst_regs[] = {
>- COMMON_GEN12BASE_ENGINE_INSTANCE(),
>+ COMMON_BASE_ENGINE_INSTANCE(),
>+};
>+
>+/* GEN9 - Global */
>+static struct __guc_mmio_reg_descr default_global_regs[] = {
>+ COMMON_BASE_GLOBAL(),
>+ COMMON_GEN9BASE_GLOBAL(),
> };
>
>-/* XE_LPD - Blitter Per-Class */
>-/* XE_LPD - Media Decode/Encode Per-Class */
>+static struct __guc_mmio_reg_descr default_rc_class_regs[] = {
>+ COMMON_BASE_HAS_EU(),
>+ COMMON_BASE_RENDER(),
>+};
>+
>+/*
>+ * Empty lists:
>+ * GEN9/XE_LPD - Blitter-Class
>+ * GEN9/XE_LPD - Media Class
>+ * GEN9 - VEC Class
>+ */
> static struct __guc_mmio_reg_descr empty_regs_list[] = {
> };
>
>@@ -130,6 +159,18 @@ static struct __guc_mmio_reg_descr empty_regs_list[] = {
> }
>
> /* List of lists */
>+static struct __guc_mmio_reg_descr_group default_lists[] = {
>+ MAKE_REGLIST(default_global_regs, PF, GLOBAL, 0),
>+ MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS),
>+ MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS),
>+ MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS),
>+ MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS),
>+ MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS),
>+ MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS),
>+ MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS),
>+ MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS),
>+ {}
>+};
> static struct __guc_mmio_reg_descr_group xe_lpd_lists[] = {
> MAKE_REGLIST(xe_lpd_global_regs, PF, GLOBAL, 0),
> MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS),
>@@ -275,7 +316,8 @@ guc_capture_get_device_reglist(struct intel_guc *guc)
> return xe_lpd_lists;
> }
>
>- return NULL;
>+ /* if GuC submission is enabled on a non-POR platform, just use a common baseline */
>+ return default_lists;
> }
>
> static const char *
>--
>2.25.1
>
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