[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display/tgl+: Implement new PLL programming step

[Patchwork]

== Series Details ==

Series: drm/i915/display/tgl+: Implement new PLL programming step
URL   : https://patchwork.freedesktop.org/series/99867/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
2f56199b0301 drm/i915/display/tgl+: Implement new PLL programming step
-:50: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#50: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2753:
+		pll_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(TGL_DPLL0_DIV0_AFC_STARTUP_OVERRIDE_VAL);

-:59: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#59: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2956:
+			pll_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(TGL_DPLL0_DIV0_AFC_STARTUP_OVERRIDE_VAL);

-:196: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#196: FILE: drivers/gpu/drm/i915/i915_reg.h:7991:
+#define TGL_DPLL0_DIV0(pll)				_MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)

-:198: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#198: FILE: drivers/gpu/drm/i915/i915_reg.h:7993:
+#define   TGL_DPLL0_DIV0_AFC_STARTUP(val)		REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))

total: 0 errors, 4 warnings, 0 checks, 160 lines checked