[Intel-gfx] [PATCH v7 1/6] drm: Add arch arm64 for drm_clflush_virt_range

[Tvrtko Ursulin]

On 09/02/2022 06:30, Michael Cheng wrote:
> Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
> performs a flush by first performing a clean, follow by an invalidation
> operation.
> 
> v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
> 		    dcache.
> 
> Signed-off-by: Michael Cheng <michael.cheng at intel.com>
> ---
>   drivers/gpu/drm/drm_cache.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> index f19d9acbe959..94b3cc3fd482 100644
> --- a/drivers/gpu/drm/drm_cache.c
> +++ b/drivers/gpu/drm/drm_cache.c
> @@ -39,6 +39,10 @@
>   /* A small bounce buffer that fits on the stack. */
>   #define MEMCPY_BOUNCE_SIZE 128
>   
> +#if defined(CONFIG_ARM64)
> +#include <asm/cacheflush.h>
> +#endif
> +

I think this likely should be a single, arch unconditional:

#include <linux/cacheflush.h>

Probably it just happens that some other include pulls in clflushopt for 
x86.

Regards,

Tvrtko

>   #if defined(CONFIG_X86)
>   #include <asm/smp.h>
>   
> @@ -176,6 +180,10 @@ drm_clflush_virt_range(void *addr, unsigned long length)
>   
>   	if (wbinvd_on_all_cpus())
>   		pr_err("Timed out waiting for cache flush\n");
> +
> +#elif defined(CONFIG_ARM64)
> +	void *end = addr + length;
> +	dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
>   #else
>   	pr_err("Architecture has no drm_cache.c support\n");
>   	WARN_ON_ONCE(1);