[Intel-gfx] [PATCH] drm/i915/dg1: Update DMC_DEBUG3 register

[Matt Roper]

On Thu, Feb 10, 2022 at 01:05:01PM +0800, Chuansheng Liu wrote:
> Current DMC_DEBUG3(_MMIO(0x101090)) address is for TGL,
> it is not wrong for DG1. Just like commit 5bcc95ca382e
> ("drm/i915/dg1: Update DMC_DEBUG register"), correct
> this issue for DG1 platform to avoid wrong register
> being read.
> 
> BSpec: 49788
> 
> Signed-off-by: Chuansheng Liu <chuansheng.liu at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 4 ++--
>  drivers/gpu/drm/i915/i915_reg.h                      | 3 ++-
>  2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index f4de004d470f..f6c4ad8fce19 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -474,8 +474,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>  		 * reg for DC3CO debugging and validation,
>  		 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
>  		 */
> -		seq_printf(m, "DC3CO count: %d\n",
> -			   intel_de_read(dev_priv, DMC_DEBUG3));
> +		seq_printf(m, "DC3CO count: %d\n", intel_de_read(dev_priv, IS_DGFX(dev_priv) ?
> +					DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3));

It looks like some future igpu platforms will likely also use this new
register offset, but those are a bit down the road; we can cross that
bridge when we get to it.  This change looks correct for now.

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

>  	} else {
>  		dc5_reg = IS_BROXTON(dev_priv) ? BXT_DMC_DC3_DC5_COUNT :
>  						 SKL_DMC_DC3_DC5_COUNT;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 87c92314ee26..9c215a6df659 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5632,7 +5632,8 @@
>  #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
>  #define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
>  
> -#define DMC_DEBUG3		_MMIO(0x101090)
> +#define TGL_DMC_DEBUG3		_MMIO(0x101090)
> +#define DG1_DMC_DEBUG3		_MMIO(0x13415c)
>  
>  /* Display Internal Timeout Register */
>  #define RM_TIMEOUT		_MMIO(0x42060)
> -- 
> 2.25.0.rc2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795