[Intel-gfx] [PATCH v5 11/19] drm/i915/lmem: Enable lmem for platforms with Flat CCS
Lucas De Marchi
lucas.demarchi at intel.com
Fri Feb 18 10:17:51 UTC 2022
On Fri, Feb 18, 2022 at 02:08:18AM -0800, Lucas De Marchi wrote:
>On Tue, Feb 01, 2022 at 04:11:24PM +0530, Ramalingam C wrote:
>>From: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
>>
>>A portion of device memory is reserved for Flat CCS so usable
>>device memory will be reduced by size of Flat CCS. Size of
>>Flat CCS is specified in “XEHPSDV_FLAT_CCS_BASE_ADDR”.
>>So to get effective device memory we need to subtract
>>total device memory by Flat CCS memory size.
>>
>>v2:
>> Addressed the small bar related issue [Matt]
>> Removed a reduntant check [Matt]
>>
>>Cc: Matthew Auld <matthew.auld at intel.com>
>>Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
>>Signed-off-by: Ramalingam C <ramalingam.c at intel.com>
>>---
>>drivers/gpu/drm/i915/gt/intel_gt.c | 19 ++++++++++++++++
>>drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
>>drivers/gpu/drm/i915/gt/intel_region_lmem.c | 24 +++++++++++++++++++--
>>drivers/gpu/drm/i915/i915_reg.h | 3 +++
>>4 files changed, 45 insertions(+), 2 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>>index f59933abbb3a..e40d98cb3a2d 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_gt.c
>>+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>>@@ -911,6 +911,25 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg)
>> return intel_uncore_read_fw(gt->uncore, reg);
>>}
>>
>>+u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg)
>>+{
>>+ int type;
>>+ u8 sliceid, subsliceid;
>>+
>>+ for (type = 0; type < NUM_STEERING_TYPES; type++) {
>>+ if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
>>+ intel_gt_get_valid_steering(gt, type, &sliceid,
>>+ &subsliceid);
>>+ return intel_uncore_read_with_mcr_steering(gt->uncore,
>>+ reg,
>>+ sliceid,
>>+ subsliceid);
>>+ }
>>+ }
>>+
>>+ return intel_uncore_read(gt->uncore, reg);
>>+}
>>+
>>void intel_gt_info_print(const struct intel_gt_info *info,
>> struct drm_printer *p)
>>{
>>diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
>>index 2dad46c3eff2..0f571c8ee22b 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_gt.h
>>+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
>>@@ -85,6 +85,7 @@ static inline bool intel_gt_needs_read_steering(struct intel_gt *gt,
>>}
>>
>>u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);
>>+u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
>>
>>void intel_gt_info_print(const struct intel_gt_info *info,
>> struct drm_printer *p);
>>diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
>>index 21215a080088..f1d37b46b505 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
>>+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
>>@@ -205,8 +205,28 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
>> if (!IS_DGFX(i915))
>> return ERR_PTR(-ENODEV);
>>
>>- /* Stolen starts from GSMBASE on DG1 */
>>- lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE);
>>+ if (HAS_FLAT_CCS(i915)) {
>>+ u64 tile_stolen, flat_ccs_base_addr_reg, flat_ccs_base;
>>+
>>+ lmem_size = pci_resource_len(pdev, 2);
>>+ flat_ccs_base_addr_reg = intel_gt_read_register(gt, XEHPSDV_FLAT_CCS_BASE_ADDR);
>
>nit since this will need a respin due to conflicts:
>we usually call _reg an i915_reg_t variable. But here you have the
>value, not the register. Maybe "flat_ccs_base_addr"?
>
>
>>+ flat_ccs_base = (flat_ccs_base_addr_reg >> XEHPSDV_CCS_BASE_SHIFT) * SZ_64K;
>>+
>>+ if (GEM_WARN_ON(lmem_size < flat_ccs_base))
>>+ return ERR_PTR(-ENODEV);
>>+
>>+ tile_stolen = lmem_size - flat_ccs_base;
>>+
>>+ /* If the FLAT_CCS_BASE_ADDR register is not populated, flag an error */
>>+ if (tile_stolen == lmem_size)
>>+ DRM_ERROR("CCS_BASE_ADDR register did not have expected value\n");
>
>drm_err()
>
>>+
>>+ lmem_size -= tile_stolen;
>>+ } else {
>>+ /* Stolen starts from GSMBASE without CCS */
>>+ lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
>>+ }
>>+
>>
>> io_start = pci_resource_start(pdev, 2);
>> if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2)))
>>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>index 0f36af8dc3a1..9b5423572fe9 100644
>>--- a/drivers/gpu/drm/i915/i915_reg.h
>>+++ b/drivers/gpu/drm/i915/i915_reg.h
>>@@ -11651,6 +11651,9 @@ enum skl_power_gate {
>>#define SGGI_DIS REG_BIT(15)
>>#define SGR_DIS REG_BIT(13)
>>
>>+#define XEHPSDV_FLAT_CCS_BASE_ADDR _MMIO(0x4910)
>>+#define XEHPSDV_CCS_BASE_SHIFT 8
>>+
>
>you will have a conflict here... I fixed it locally by moving to
>gt/intel_gt_regs.h
>
>
>With the above,
>
>Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
Also, I may be wrong and couldn't test it today. But... to finally have BAT
on CI working, this and "drm/i915/xehpsdv: Add has_flat_ccs to device info" are
the only changes from the FlatCCS part that are strictly
needed, isn't it?
"drm/i915/migrate: add acceleration support for DG2", all the plane
format, support for clearing ccs etc are things that could be on top.
Lucas De Marchi
>
>Lucas De Marchi
>
>>/* gamt regs */
>>#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
>>#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
>>--
>>2.20.1
>>
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