[Intel-gfx] [PATCH 0/2] drm/i915/dg2: Do not use phy E

Lucas De Marchi lucas.demarchi at intel.com
Sat Feb 19 04:09:52 UTC 2022

On Fri, Feb 18, 2022 at 01:54:36AM -0800, Lucas De Marchi wrote:
>This is an alternative to
>("drm/i915/dg2: 5th Display output").

After talking with Matt Roper, it seems the issue calibrating the phy
happens sporadically on any phy. So, there isn't anything special with
phy E here.

Therefore, let's just go with the patch series adding the 5th port.

Applied the other series.

Lucas De Marchi

>We tried to enable the 5th port in order to get rid of
>the unclaimed register access, but even after the basic plumbing, we
>are still getting and error that the phy failed to calibrate.
>So, rather than enabling it and needing another fix on top later, let's
>just fix the immediate issue: we are initializing only 4 ports/phys, but
>intel_phy_is_snps() returns we have 5, so we access registers we
>I'm still bringing "drm/i915/dg2: Drop 38.4 MHz MPLLB tables", as that
>is just eliminating dead code.
>Lucas De Marchi (1):
>  drm/i915/dg2: Do not use phy E
>Matt Roper (1):
>  drm/i915/dg2: Drop 38.4 MHz MPLLB tables
> drivers/gpu/drm/i915/display/intel_display.c  |   5 +-
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 208 +-----------------
> 2 files changed, 4 insertions(+), 209 deletions(-)

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