[Intel-gfx] [PATCH v12 1/6] drm: Add arch arm64 for drm_clflush_virt_range

[Tvrtko Ursulin]

On 25/02/2022 03:24, Michael Cheng wrote:
> Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou
> performs a flush by first performing a clean, follow by an invalidation
> operation.
> 
> v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
> 		    dcache. Thanks Tvrtko for the suggestion.
> 
> v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
> 
> v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a
> 		    symbol that could be use by other modules, thus use
> 		    caches_clean_inval_pou instead. Also this version
> 	            removes include for cacheflush, since its already
> 		    included base on architecture type.

What does it mean that it is included based on architecture type? Some 
of the other header already pulls it in?

Regards,

Tvrtko

> Signed-off-by: Michael Cheng <michael.cheng at intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>   drivers/gpu/drm/drm_cache.c | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> index c3e6e615bf09..81c28714f930 100644
> --- a/drivers/gpu/drm/drm_cache.c
> +++ b/drivers/gpu/drm/drm_cache.c
> @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length)
>   
>   	if (wbinvd_on_all_cpus())
>   		pr_err("Timed out waiting for cache flush\n");
> +
> +#elif defined(CONFIG_ARM64)
> +	void *end = addr + length;
> +	caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
> +
>   #else
>   	WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
>   #endif