[Intel-gfx] [PATCH 0/4] Async flip optimization for DG2

[Stanislav Lisovskiy]

Limitting the WM levels to 0 for DG2 during async flips,
allows to slightly increase the performance, as recommended
by HW team.

Stanislav Lisovskiy (4):
  drm/i915: Pass plane to watermark calculation functions
  drm/i915: Introduce do_async_flip flag to intel_plane_state
  drm/i915: Use wm0 only during async flips for DG2
  drm/i915: Don't allocate extra ddb during async flip for DG2

 .../gpu/drm/i915/display/intel_atomic_plane.c |  5 +-
 .../gpu/drm/i915/display/intel_atomic_plane.h |  4 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 31 ++++++-
 .../drm/i915/display/intel_display_types.h    |  3 +
 drivers/gpu/drm/i915/intel_pm.c               | 83 ++++++++++++++-----
 5 files changed, 102 insertions(+), 24 deletions(-)

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2.24.1.485.gad05a3d8e5