[Intel-gfx] [PATCH] drm/i915/guc: Update guc shim control programming on newer platforms

[Belgaumkar, Vinay]

On 1/20/2022 2:24 PM, Daniele Ceraolo Spurio wrote:
> Starting from xehpsdv, bit 0 of of the GuC shim control register has
> been repurposed, while bit 2 is now reserved, so we need to avoid
> setting those for their old meaning on newer platforms.
>
> Cc: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
> Cc: Stuart Summers <stuart.summers at intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> ---
>   drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 8 +++++---
>   1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> index f773e7f35bc1a..40f7d4779c9ec 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> @@ -15,13 +15,15 @@
>   
>   static void guc_prepare_xfer(struct intel_uncore *uncore)
>   {
> -	u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
> -			 GUC_ENABLE_READ_CACHE_LOGIC |
> -			 GUC_ENABLE_MIA_CACHING |
> +	u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |
>   			 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
>   			 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
>   			 GUC_ENABLE_MIA_CLOCK_GATING;
>   
> +	if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50))
> +		shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
> +			      GUC_ENABLE_MIA_CACHING;
> +

LGTM.

Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar at intel.com>

>   	/* Must program this register before loading the ucode with DMA */
>   	intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
>