[Intel-gfx] [PATCH v2 4/6] drm/i915: Parameterize MI_PREDICATE registers

[Lucas De Marchi]

On Mon, Jan 24, 2022 at 06:08:24PM -0800, Matt Roper wrote:
>The various MI_PREDICATE registers have per-engine instances.  Today we
>only utilize the RCS0 instance of each, but that will likely change in
>the future; switch to parameterized register definitions to make these
>easier to work with going forward.
>
>Of special note is MI_PREDICATE_RESULT_2; we only use it in one place in
>the driver today in HSW-specific code.  It turns out that the bspec
>(page 94) lists two different offsets for this register on HSW; one is
>in the standard location shared by all other platforms (base + 0x3bc)
>and the other is an unusual location (0x2214).  We're using the second,
>non-standard offset in i915 today; that offset doesn't exist on any
>other platforms (and it's not even 100% clear that it's correct for HSW)
>so I've renamed the current non-standard definition to
>HSW_MI_PREDICATE_RESULT_2; the new cross-platform parameterized macro
>(which is still unused at the moment) uses the standard offset.
>
>Cc: Jani Nikula <jani.nikula at intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi