[Intel-gfx] [PATCH v2 5/6] drm/i915: Move GT registers to their own header file

[Lucas De Marchi]

On Mon, Jan 24, 2022 at 06:08:25PM -0800, Matt Roper wrote:
>+#define MEMSWCTL		_MMIO(0x11170) /* Ironlake only */
>+#define   MEMCTL_CMD_MASK	0xe000
>+#define   MEMCTL_CMD_SHIFT	13
>+#define   MEMCTL_CMD_RCLK_OFF	0
>+#define   MEMCTL_CMD_RCLK_ON	1
>+#define   MEMCTL_CMD_CHFREQ	2
>+#define   MEMCTL_CMD_CHVID	3
>+#define   MEMCTL_CMD_VMMOFF	4
>+#define   MEMCTL_CMD_VMMON	5
>+#define   MEMCTL_CMD_STS	(1 << 12) /* write 1 triggers command, clears
>+when command complete */

formatting issue here

>+#define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice) * 0x4)
>+#define GEN10_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + ((slice) / 3) * 0x34 + \
>+((slice) % 3) * 0x4)

and here

>+#define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
>+#define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice) * 2))
>+#define   GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
>+
>+#define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice) * 0x8)
>+#define GEN10_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + ((slice) / 3) * 0x30 + \
>+((slice) % 3) * 0x8)

and here

>+#define GEN9_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + (slice) * 0x8)
>+#define GEN10_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + ((slice) / 3) * 0x30 + \
>+((slice) % 3) * 0x8)

and here.


Rest looks sane. There's already a conflict in this patch, although
following "this should be just code move",  it's easy to solve.


I wonder what is the strategy going to be for merging this because it
will conflict badly between drm-intel-next and drm-intel-gt-next.


Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi