[Intel-gfx] [PATCH 1/2] drm/i915/gt: Re-work intel_write_status_page

[Bowman, Casey G]

> -----Original Message-----
> From: Cheng, Michael <michael.cheng at intel.com>
> Sent: Thursday, January 27, 2022 3:41 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: Cheng, Michael <michael.cheng at intel.com>; Bowman, Casey G
> <casey.g.bowman at intel.com>; De Marchi, Lucas
> <lucas.demarchi at intel.com>; Boyer, Wayne <wayne.boyer at intel.com>;
> ville.syrjala at linux.intel.com; Kuoppala, Mika <mika.kuoppala at intel.com>;
> chris at chris-wilson.co.uk
> Subject: [PATCH 1/2] drm/i915/gt: Re-work intel_write_status_page
> 
> Re-work intel_write_status_page to use drm_clflush_virt_range. This will
> prevent compiler errors when building for non-x86 architectures.
> 
> Signed-off-by: Michael Cheng <michael.cheng at intel.com>

Reviewed-by: Casey Bowman <casey.g.bowman at intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
>  1 file changed, 4 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 08559ace0ada..e6189fffa7a3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -4,6 +4,7 @@
> 
>  #include <asm/cacheflush.h>
>  #include <drm/drm_util.h>
> +#include <drm/drm_cache.h>
> 
>  #include <linux/hashtable.h>
>  #include <linux/irq_work.h>
> @@ -144,15 +145,9 @@ intel_write_status_page(struct intel_engine_cs
> *engine, int reg, u32 value)
>  	 * of extra paranoia to try and ensure that the HWS takes the value
>  	 * we give and that it doesn't end up trapped inside the CPU!
>  	 */
> -	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
> -		mb();
> -		clflush(&engine->status_page.addr[reg]);
> -		engine->status_page.addr[reg] = value;
> -		clflush(&engine->status_page.addr[reg]);
> -		mb();
> -	} else {
> -		WRITE_ONCE(engine->status_page.addr[reg], value);
> -	}
> +	drm_clflush_virt_range(&engine->status_page.addr[reg],
> PAGE_SIZE);
> +	WRITE_ONCE(engine->status_page.addr[reg], value);
> +	drm_clflush_virt_range(&engine->status_page.addr[reg],
> PAGE_SIZE);
>  }
> 
>  /*
> --
> 2.25.1