[Intel-gfx] [PATCH v2 12/17] drm/i915: Fix intel_cpu_transcoder_has_m2_n2()

[Ville Syrjälä]

On Mon, Jan 31, 2022 at 05:05:53PM +0200, Jani Nikula wrote:
> On Fri, 28 Jan 2022, Ville Syrjala <ville.syrjala at linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> >
> > M2/N2 values are present for all ilk-ivb,vlv,chv (and hsw edp).
> > Make the code reflect that.
> 
> Nitpick, it's not called intel_cpu_transcoder_has_m2_n2() until in the
> next patch.
> 
> Side note, I've also been looking at this bit in intel_drrs_set_state():
> 
> 	if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv))
> 		intel_drrs_set_refresh_rate_m_n(crtc_state, refresh_type);
> 	else if (DISPLAY_VER(dev_priv) > 6)
> 		intel_drrs_set_refresh_rate_pipeconf(crtc_state, refresh_type);
> 
> and wondering if that should be deduplicated with the
> transcoder_has_m2_n2() somehow. This is all a bit confusing with the
> slightly different conditions.

Yeah, I have a patch to use intel_cpu_transcoder_has_m2_n2() for
this already on my drrs branch. It just didn't make the cut for
this series for some arbitrary reason.

The other place we could perhaps use intel_cpu_transcoder_has_m2_n2()
is the PIPE_CONF_CHECK_ALT vs. checking both m_n and m2_n2. But I don't
really want the logic there to depend on the states it's trying to
compare, so I think a naked platform check there is better.

-- 
Ville Syrjälä
Intel