[Intel-gfx] [PATCH 1/1] drm/i915/dg2: Bump up CDCLK for DG2

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Stanislav
> Lisovskiy
> Sent: Tuesday, June 14, 2022 6:01 PM
> To: intel-gfx at lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 1/1] drm/i915/dg2: Bump up CDCLK for DG2
> 
> We seem to need this W/A same way as for TGL, in order to fix some of the
> underruns, which we currently have and those not related to PSR.

We need to dig deeper on the real root causes and try to identify scenarios restricted by
hardware bandwidth limits and operate at optimum CD clock.

This should be kept under investigation with some open JIRA ticket while we can get the
tree stabilized with this stop gap solution.

With above agreed, this is:
Reviewed-by: Uma Shankar <uma.shankar at intel.com>

> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 6e80162632dd..86a22c3766e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2300,7 +2300,7 @@ int intel_crtc_compute_min_cdclk(const struct
> intel_crtc_state *crtc_state)
>  		min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
> 
>  	/*
> -	 * HACK. Currently for TGL platforms we calculate
> +	 * HACK. Currently for TGL/DG2 platforms we calculate
>  	 * min_cdclk initially based on pixel_rate divided
>  	 * by 2, accounting for also plane requirements,
>  	 * however in some cases the lowest possible CDCLK @@ -2308,7 +2308,7
> @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	 * Explicitly stating here that this seems to be currently
>  	 * rather a Hack, than final solution.
>  	 */
> -	if (IS_TIGERLAKE(dev_priv)) {
> +	if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) {
>  		/*
>  		 * Clamp to max_cdclk_freq in case pixel rate is higher,
>  		 * in order not to break an 8K, but still leave W/A at place.
> --
> 2.24.1.485.gad05a3d8e5