[Intel-gfx] [PATCH] drm/i915/tgl+: Fix HDMI transcoder clock vs. DDI BUF disabling order

[Nautiyal, Ankit K]

Change is according to the specs. I see similar thing for DP as well, 
and its already taken care in disable DP path,

seems like it was missing only for HDMI.

LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>

On 6/17/2022 4:58 PM, Imre Deak wrote:
> Starting with TGL the disabling order of HDMI transcoder clock vs. DDI
> BUF has swapped, fix this. There hasn't been any issues seen related to
> this, but let's follow the spec.
>
> Reported-by: Sandeep K Lakkakula <sandeep.k.lakkakula at intel.com>
> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 272e1bf6006be..4b874c31398a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2691,10 +2691,14 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
>   	dig_port->set_infoframes(encoder, false,
>   				 old_crtc_state, old_conn_state);
>   
> -	intel_ddi_disable_pipe_clock(old_crtc_state);
> +	if (DISPLAY_VER(dev_priv) < 12)
> +		intel_ddi_disable_pipe_clock(old_crtc_state);
>   
>   	intel_disable_ddi_buf(encoder, old_crtc_state);
>   
> +	if (DISPLAY_VER(dev_priv) >= 12)
> +		intel_ddi_disable_pipe_clock(old_crtc_state);
> +
>   	intel_display_power_put(dev_priv,
>   				dig_port->ddi_io_power_domain,
>   				fetch_and_zero(&dig_port->ddi_io_wakeref));