[Intel-gfx] [PATCH v2 3/3] drm/i915: Parse max link rate from the eDP BDB block

[Jani Nikula]

On Thu, 02 Jun 2022, Ville Syrjala <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> The eDP BDB block has gained yet another max link rate field.
> Let's parse it and consult it during the source rate filtering.
>
> v2: *20 instead of *2 to get the correct units (Jani)

Failed to mention the same issue here as in the previous patch, but
yeah. :)

BR,
Jani.

>
> Reviewed-by: Jani Nikula <jani.nikula at intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c     |  4 ++++
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 23 +++++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  1 +
>  4 files changed, 27 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 425e91d8cd2f..aaea27fe5d16 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1461,6 +1461,10 @@ parse_edp(struct drm_i915_private *i915,
>  
>  	panel->vbt.edp.drrs_msa_timing_delay =
>  		(edp->sdrrs_msa_timing_delay >> (panel_type * 2)) & 3;
> +
> +	if (i915->vbt.version >= 244)
> +		panel->vbt.edp.max_link_rate =
> +			edp->edp_max_port_link_rate[panel_type] * 20;
>  }
>  
>  static void
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9b44358e8d9e..8b0949b6dc75 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -300,6 +300,7 @@ struct intel_vbt_panel_data {
>  	enum drrs_type drrs_type;
>  
>  	struct {
> +		int max_link_rate;
>  		int rate;
>  		int lanes;
>  		int preemphasis;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 03af93ef9e93..8ff875ab3b37 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -408,6 +408,26 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp)
>  	return 810000;
>  }
>  
> +static int vbt_max_link_rate(struct intel_dp *intel_dp)
> +{
> +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> +	int max_rate;
> +
> +	max_rate = intel_bios_dp_max_link_rate(encoder);
> +
> +	if (intel_dp_is_edp(intel_dp)) {
> +		struct intel_connector *connector = intel_dp->attached_connector;
> +		int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
> +
> +		if (max_rate && edp_max_rate)
> +			max_rate = min(max_rate, edp_max_rate);
> +		else if (edp_max_rate)
> +			max_rate = edp_max_rate;
> +	}
> +
> +	return max_rate;
> +}
> +
>  static void
>  intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
> @@ -429,7 +449,6 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  		162000, 270000
>  	};
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> -	struct intel_encoder *encoder = &dig_port->base;
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>  	const int *source_rates;
>  	int size, max_rate = 0, vbt_max_rate;
> @@ -465,7 +484,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  		size = ARRAY_SIZE(g4x_rates);
>  	}
>  
> -	vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
> +	vbt_max_rate = vbt_max_link_rate(intel_dp);
>  	if (max_rate && vbt_max_rate)
>  		max_rate = min(max_rate, vbt_max_rate);
>  	else if (vbt_max_rate)
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 58aee0a040cf..f8e5097222f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -697,6 +697,7 @@ struct bdb_edp {
>  	u16 apical_enable;					/* 203 */
>  	struct edp_apical_params apical_params[16];		/* 203 */
>  	u16 edp_fast_link_training_rate[16];			/* 224 */
> +	u16 edp_max_port_link_rate[16];				/* 244 */
>  } __packed;
>  
>  /*

-- 
Jani Nikula, Intel Open Source Graphics Center