[Intel-gfx] [RFC PATCH 0/3] Get dsc optimal output bpp
Ankit Nautiyal
ankit.k.nautiyal at intel.com
Thu Jun 16 04:22:44 UTC 2022
Currently, when going with DSC for DP, we take the max lane, rate
and pipe bpp, to get the maximum compressed bpp possible. We then
set the output bpp to this value. It might be possible to have lesser
rate or lane count, for which the same compressed bpp works.
This RFC series attempts to get the best compressed bpp such that we
have maximum bpc, with minimum link rate and lane possible.
The policy here is chosen such that 'best compressed bpp' mean minimum
compression, ie. maximum compressed bpp. It means compress only that
is sufficient to sent over the link, and for that compressed bpp,
use minimum lanes, and rate.
Current series, only touches the DSC for DisplayPort. eDP might require
some more changes and also a different policy.
Ankit Nautiyal (3):
drm/i915/dp: Rename helper to calculate dsc output bpp
drm/i915/dp: Rename helper to get max pipe bpp with DSC
drm/i915/dp: Get optimal link config to have best compressed bpp
drivers/gpu/drm/i915/display/intel_dp.c | 263 ++++++++++++++++++------
1 file changed, 201 insertions(+), 62 deletions(-)
--
2.25.1
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