[Intel-gfx] [PATCH 1/2] drm/i915: Correct duplicated/misplaced GT register definitions

[Lucas De Marchi]

On Fri, Jun 24, 2022 at 02:03:27PM -0700, Matt Roper wrote:
>XEHPSDV_FLAT_CCS_BASE_ADDR, GEN8_L3_LRA_1_GPGPU, and MMCD_MISC_CTRL were
>duplicated between i915_reg.h and intel_gt_regs.h.  These are all GT
>registers, so we should drop the copy from i915_reg.h.
>
>XEHPSDV_TILE0_ADDR_RANGE was defined in i915_reg.h, but really belongs
>in intel_gt_regs.h.  Move it.
>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi <lucas.demarchi at intel.com>

>---
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c |  1 +
> drivers/gpu/drm/i915/gt/intel_gt_regs.h    |  3 +++
> drivers/gpu/drm/i915/i915_reg.h            | 17 -----------------
> 3 files changed, 4 insertions(+), 17 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>index fa54823d1219..e63de9c06596 100644
>--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>@@ -14,6 +14,7 @@
> #include "gem/i915_gem_region.h"
> #include "gt/intel_gt.h"
> #include "gt/intel_gt_mcr.h"
>+#include "gt/intel_gt_regs.h"
> #include "gt/intel_region_lmem.h"
> #include "i915_drv.h"
> #include "i915_gem_stolen.h"
>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>index 07ef111947b8..61815b6e87de 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>@@ -324,6 +324,9 @@
>
> #define GEN12_PAT_INDEX(index)			_MMIO(0x4800 + (index) * 4)
>
>+#define XEHPSDV_TILE0_ADDR_RANGE		_MMIO(0x4900)
>+#define   XEHPSDV_TILE_LMEM_RANGE_SHIFT		8
>+
> #define XEHPSDV_FLAT_CCS_BASE_ADDR		_MMIO(0x4910)
> #define   XEHPSDV_CCS_BASE_SHIFT		8
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 932bd6aa4a0a..cf5e16abf6c7 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -8345,23 +8345,6 @@ enum skl_power_gate {
> #define   SGGI_DIS			REG_BIT(15)
> #define   SGR_DIS			REG_BIT(13)
>
>-#define XEHPSDV_TILE0_ADDR_RANGE	_MMIO(0x4900)
>-#define   XEHPSDV_TILE_LMEM_RANGE_SHIFT  8
>-
>-#define XEHPSDV_FLAT_CCS_BASE_ADDR	_MMIO(0x4910)
>-#define   XEHPSDV_CCS_BASE_SHIFT	8
>-
>-/* gamt regs */
>-#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
>-#define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
>-#define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV  0x5FF101FF /* max/min for LRA1/2 */
>-#define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL  0x67F1427F /*    "        " */
>-#define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT  0x5FF101FF /*    "        " */
>-
>-#define MMCD_MISC_CTRL		_MMIO(0x4ddc) /* skl+ */
>-#define  MMCD_PCLA		(1 << 31)
>-#define  MMCD_HOTSPOT_EN	(1 << 27)
>-
> #define _ICL_PHY_MISC_A		0x64C00
> #define _ICL_PHY_MISC_B		0x64C04
> #define _DG2_PHY_MISC_TC1	0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
>-- 
>2.36.1
>