[Intel-gfx] [PATCH] drm/i915: tweak the ordering in cpu_write_needs_clflush

[Gwan-gyeong Mun]

Thanks for fixing this issue.
Looks good to me.

Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>

On 6/22/22 6:59 PM, Matthew Auld wrote:
> For imported dma-buf objects we leave the object as cache_coherent = 0
> across all platforms, which is reasonable given that have no clue what
> the memory underneath is, and its not like the driver can ever manually
> clflush the pages anyway (like with i915_gem_clflush_object) for such
> objects. However on discrete we choose to treat cache_dirty = true as a
> programmer error, leading to a warning. The simplest fix looks to be to
> just change the ordering in cpu_write_needs_clflush to prevent ever
> setting cache_dirty for dma-buf objects on discrete.
> 
> Fixes: d028a7690d87 ("drm/i915/dmabuf: Fix prime_mmap to work when using LMEM")
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5266
> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
> Cc: Thomas Hellström <thomas.hellstrom at linux.intel.com>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>
> ---
>   drivers/gpu/drm/i915/gem/i915_gem_domain.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> index 3e5d6057b3ef..1674b0c5802b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> @@ -35,12 +35,12 @@ bool i915_gem_cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
>   	if (obj->cache_dirty)
>   		return false;
>   
> -	if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
> -		return true;
> -
>   	if (IS_DGFX(i915))
>   		return false;
>   
> +	if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
> +		return true;
> +
>   	/* Currently in use by HW (display engine)? Keep flushed. */
>   	return i915_gem_object_is_framebuffer(obj);
>   }
>