[Intel-gfx] [PATCH] drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities

[Ville Syrjälä]

On Mon, Feb 28, 2022 at 10:12:34PM +0200, Imre Deak wrote:
> At least some DELL monitors (P2715Q) with DPCD_REV 1.2 return corrupted
> DPCD register values when reading from the 0xF0000- LTTPR range with an
> AUX transaction block size bigger than 1. The DP standard requires 0 to
> be returned - as for any other reserved/invalid addresses - but these
> monitors return the DPCD_REV register value repeated in each byte of the
> read buffer. This will in turn corrupt the values returned by the LTTPRs
> between the source and the monitor: LTTPRs must adjust the values they
> read from the downstream DPRX, for instance left-shift/init the
> downstream DP_PHY_REPEATER_CNT value. Since the value returned by the
> monitor's DPRX is non-zero the adjusted values will be corrupt.
> 
> Reading the LTTPR registers one-by-one instead of reading all of them
> with a single AUX transfer works around the issue.
> 
> According to the DP standard's 0xF0000 register description:
> "LTTPR-related registers at DPCD Addresses F0000h through F02FFh are
> valid only for DPCD r1.4 (or higher)." While it's unclear if DPCD r1.4
> refers to the DPCD_REV or to the
> LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV register (tickets filed
> at the VESA site to clarify this haven't been addressed), one
> possibility is that it's a restriction due to non-compliant monitors
> described above. Disabling the non-transparent LTTPR mode for all such
> monitors is not a viable solution: the transparent LTTPR mode has its
> own issue causing link training failures and this would affect a lot of
> monitors in use with DPCD_REV < 1.4. Instead this patch works around
> the problem by reading the LTTPR common and PHY cap registers one-by-one
> for any monitor with a DPCD_REV < 1.4.
> 
> The standard requires the DPCD capabilites to be read after the LTTPR
> common capabilities are read, so re-read the DPCD capabilities after
> the LTTPR common and PHY caps were read out.
> 
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4531
> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
>  drivers/gpu/drm/dp/drm_dp.c                   | 58 ++++++++++++-------
>  .../drm/i915/display/intel_dp_link_training.c | 30 +++++++---
>  include/drm/dp/drm_dp_helper.h                |  2 +
>  3 files changed, 59 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
> index 703972ae14c64..f3950d42980f9 100644
> --- a/drivers/gpu/drm/dp/drm_dp.c
> +++ b/drivers/gpu/drm/dp/drm_dp.c
> @@ -2390,9 +2390,36 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>  }
>  EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
>  
> +static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
> +				  u8 *buf, int buf_size)
> +{
> +	/*
> +	 * Some monitors with a DPCD_REV < 0x14 return corrupted values when
> +	 * reading from the 0xF0000- range with a block size bigger than 1.
> +	 */

This sounds really scary. Have we checked what other registers might
end up corrupted? Eg. couple of rounds of comparing full dd bs=1 vs. 
dd bs=16.

> +	int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
> +	int offset = 0;
> +	int ret;
> +
> +	while (offset < buf_size) {

Can we use a for loop?

> +		ret = drm_dp_dpcd_read(aux,
> +				       address + offset,
> +				       &buf[offset], block_size);
> +		if (ret < 0)
> +			return ret;
> +
> +		WARN_ON(ret != block_size);
> +
> +		offset += block_size;
> +	}
> +
> +	return 0;
> +}
> +

-- 
Ville Syrjälä
Intel