[Intel-gfx] [PATCH v2 0/9] drm/i915: Fix bandwith related cdclk calculations

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

Fix up the dbuf bandwidth cdclk calculations to match the spec,
and also implement the cdclk based pipe max bandwidth limit.

TODO: intel_bw contains two orthogonal things (qgv vs. cdclk).
      We should probably just split it into two parts to life
      less confusing. But as usual naming is hard so I didn't
      go for that yet...

v2: Rebased due to the async flip wm0/ddb stuff

Ville Syrjälä (9):
  drm/i915: Tweak plane ddb allocation tracking
  drm/i915: Split plane data_rate into data_rate+data_rate_y
  drm/i915: Pre-calculate plane relative data rate
  drm/i915: Remove total[] and uv_total[] from ddb allocation
  drm/i915: Nuke intel_bw_calc_min_cdclk()
  drm/i915: Round up when calculating display bandwidth requirements
  drm/i915: Properly write lock bw_state when it changes
  drm/i915: Fix DBUF bandwidth vs. cdclk handling
  drm/i915: Add "maximum pipe read bandwidth" checks

 .../gpu/drm/i915/display/intel_atomic_plane.c | 120 ++++--
 .../gpu/drm/i915/display/intel_atomic_plane.h |   3 +-
 drivers/gpu/drm/i915/display/intel_bw.c       | 254 ++++++++-----
 drivers/gpu/drm/i915/display/intel_bw.h       |  12 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  96 ++---
 drivers/gpu/drm/i915/display/intel_cdclk.h    |   2 +
 drivers/gpu/drm/i915/display/intel_display.c  |  17 +-
 .../drm/i915/display/intel_display_debugfs.c  |   4 +-
 .../drm/i915/display/intel_display_types.h    |  16 +-
 drivers/gpu/drm/i915/intel_pm.c               | 359 ++++++------------
 10 files changed, 431 insertions(+), 452 deletions(-)

-- 
2.34.1