[Intel-gfx] [PATCH v2 2/8] drm/i915: Remove redundant/wrong comments

[Jani Nikula]

On Tue, 08 Mar 2022, Ville Syrjala <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Remove the comment specifying the exact formulat for calculating
> the DPLL frequency from the *_find_best_dpll() functions. Each
> platform variant has its own way to calculate these and we have
> the code already to do that. These comments are entirely redundant
> and often even wrong so just get rid of them.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Acked-by: Jani Nikula <jani.nikula at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 15 +++++----------
>  1 file changed, 5 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index b3fd94538c44..f4e5290b86a4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -425,8 +425,7 @@ i9xx_select_p2_div(const struct intel_limit *limit,
>  
>  /*
>   * Returns a set of divisors for the desired target clock with the given
> - * refclk, or FALSE.  The returned values represent the clock equation:
> - * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
> + * refclk, or FALSE.
>   *
>   * Target and reference clocks are specified in kHz.
>   *
> @@ -484,8 +483,7 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
>  
>  /*
>   * Returns a set of divisors for the desired target clock with the given
> - * refclk, or FALSE.  The returned values represent the clock equation:
> - * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
> + * refclk, or FALSE.
>   *
>   * Target and reference clocks are specified in kHz.
>   *
> @@ -541,8 +539,7 @@ pnv_find_best_dpll(const struct intel_limit *limit,
>  
>  /*
>   * Returns a set of divisors for the desired target clock with the given
> - * refclk, or FALSE.  The returned values represent the clock equation:
> - * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
> + * refclk, or FALSE.
>   *
>   * Target and reference clocks are specified in kHz.
>   *
> @@ -641,8 +638,7 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
>  
>  /*
>   * Returns a set of divisors for the desired target clock with the given
> - * refclk, or FALSE.  The returned values represent the clock equation:
> - * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
> + * refclk, or FALSE.
>   */
>  static bool
>  vlv_find_best_dpll(const struct intel_limit *limit,
> @@ -700,8 +696,7 @@ vlv_find_best_dpll(const struct intel_limit *limit,
>  
>  /*
>   * Returns a set of divisors for the desired target clock with the given
> - * refclk, or FALSE.  The returned values represent the clock equation:
> - * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
> + * refclk, or FALSE.
>   */
>  static bool
>  chv_find_best_dpll(const struct intel_limit *limit,

-- 
Jani Nikula, Intel Open Source Graphics Center