[Intel-gfx] [PATCH 05/13] drm/i915: Program MSA timing delay on ilk/snb/ivb

[Jani Nikula]

On Thu, 10 Mar 2022, Ville Syrjala <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Grab the DRRS MSA timing delay value from the VBT
> and program things accordingly. Only ilk/snb/ivb have
> this so presumably on hsw+ we don't need it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c       | 8 ++++++--
>  drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
>  drivers/gpu/drm/i915/display/intel_drrs.c          | 3 +++
>  drivers/gpu/drm/i915/i915_reg.h                    | 2 ++
>  4 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 54db81c2cce6..b7c418677372 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3577,6 +3577,7 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
>  
>  	val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
> +	val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
>  
>  	intel_de_write(dev_priv, PIPECONF(pipe), val);
>  	intel_de_posting_read(dev_priv, PIPECONF(pipe));
> @@ -3865,6 +3866,8 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
>  
>  	pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
>  
> +	pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp);
> +
>  	pipe_config->csc_mode = intel_de_read(dev_priv,
>  					      PIPE_CSC_MODE(crtc->pipe));
>  
> @@ -5345,8 +5348,8 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
>  				      &pipe_config->dp_m2_n2);
>  	}
>  
> -	drm_dbg_kms(&dev_priv->drm, "framestart delay: %d\n",
> -		    pipe_config->framestart_delay);
> +	drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n",
> +		    pipe_config->framestart_delay, pipe_config->msa_timing_delay);
>  
>  	drm_dbg_kms(&dev_priv->drm,
>  		    "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
> @@ -6243,6 +6246,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	PIPE_CONF_CHECK_X(output_types);
>  
>  	PIPE_CONF_CHECK_I(framestart_delay);
> +	PIPE_CONF_CHECK_I(msa_timing_delay);
>  
>  	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
>  	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5e8d7394a394..86b2fa675124 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1155,6 +1155,7 @@ struct intel_crtc_state {
>  	u8 update_planes;
>  
>  	u8 framestart_delay; /* 1-4 */
> +	u8 msa_timing_delay; /* 0-3 */
>  
>  	struct {
>  		u32 enable;
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
> index 17bedecbd7b2..5b3711fe0674 100644
> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -83,6 +83,9 @@ intel_drrs_compute_config(struct intel_dp *intel_dp,
>  		return;
>  	}
>  
> +	if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
> +		pipe_config->msa_timing_delay = i915->vbt.edp.drrs_msa_timing_delay;
> +
>  	pipe_config->has_drrs = true;
>  
>  	pixel_clock = connector->panel.downclock_mode->clock;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 70484f6f2b8b..c106fb23e245 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3706,6 +3706,8 @@
>  #define   PIPECONF_INTERLACE_IF_ID_DBL_ILK	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
>  #define   PIPECONF_INTERLACE_PF_ID_DBL_ILK	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
>  #define   PIPECONF_EDP_RR_MODE_SWITCH		REG_BIT(20)
> +#define   PIPECONF_MSA_TIMING_DELAY_MASK	REG_GENMASK(19, 18) /* ilk/snb/ivb */
> +#define   PIPECONF_MSA_TIMING_DELAY(x)		REG_FIELD_PREP(PIPECONF_MSA_TIMING_DELAY_MASK, (x))
>  #define   PIPECONF_CXSR_DOWNCLOCK		REG_BIT(16)
>  #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	REG_BIT(14)
>  #define   PIPECONF_COLOR_RANGE_SELECT		REG_BIT(13)

-- 
Jani Nikula, Intel Open Source Graphics Center