[Intel-gfx] [PATCH 2/8] drm/i915/dmc: move assert_dmc_loaded() to intel_dmc.c

[Lucas De Marchi]

On Thu, Mar 17, 2022 at 08:36:14PM +0200, Jani Nikula wrote:
>Start localizing DMC register and data access to intel_dmc.c.
>
>Signed-off-by: Jani Nikula <jani.nikula at intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display_power.c | 12 ------------
> drivers/gpu/drm/i915/display/intel_dmc.c           | 11 +++++++++++
> drivers/gpu/drm/i915/display/intel_dmc.h           |  2 ++
> 3 files changed, 13 insertions(+), 12 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>index b3efe345567f..6a5695008f7c 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>@@ -905,18 +905,6 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
> 	intel_pps_unlock_regs_wa(dev_priv);
> }
>
>-static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
>-{
>-	drm_WARN_ONCE(&dev_priv->drm,
>-		      !intel_de_read(dev_priv,
>-				     DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
>-				     "DMC program storage start is NULL\n");
>-	drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
>-		      "DMC SSP Base Not fine\n");
>-	drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
>-		      "DMC HTP Not fine\n");
>-}
>-
> /**
>  * intel_display_power_set_target_dc_state - Set target dc state.
>  * @dev_priv: i915 device
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index 66fd69259e73..63ae16622c3e 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -305,6 +305,17 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> 	gen9_set_dc_state_debugmask(dev_priv);
> }
>
>+void assert_dmc_loaded(struct drm_i915_private *i915)
>+{
>+	drm_WARN_ONCE(&i915->drm,
>+		      !intel_de_read(i915, DMC_PROGRAM(i915->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
>+		      "DMC program storage start is NULL\n");
>+	drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE),
>+		      "DMC SSP Base Not fine\n");
>+	drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL),
>+		      "DMC HTP Not fine\n");
>+}
>+
> static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
> 				     const struct stepping_info *si)
> {
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
>index 7c590309a3a9..326f80ad0f31 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.h
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
>@@ -55,4 +55,6 @@ void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
> void intel_dmc_ucode_resume(struct drm_i915_private *i915);
> bool intel_dmc_has_payload(struct drm_i915_private *i915);
>
>+void assert_dmc_loaded(struct drm_i915_private *i915);


intel_dmc_assert_loaded()?

Lucas De Marchi

>+
> #endif /* __INTEL_DMC_H__ */
>-- 
>2.30.2
>