[Intel-gfx] [PATCH 8/8] drm/i915/dmc: split out dmc registers to a separate file

[Lucas De Marchi]

On Thu, Mar 17, 2022 at 08:36:20PM +0200, Jani Nikula wrote:
>Clean up the massive i915_reg.h a bit with this isolated set of
>registers.
>
>Signed-off-by: Jani Nikula <jani.nikula at intel.com>
>---
> drivers/gpu/drm/i915/display/intel_dmc.c      |  1 +
> drivers/gpu/drm/i915/display/intel_dmc_regs.h | 31 +++++++++++++++++++
> drivers/gpu/drm/i915/gvt/handlers.c           |  1 +
> drivers/gpu/drm/i915/i915_reg.h               | 21 -------------
> 4 files changed, 33 insertions(+), 21 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_regs.h
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index 7b7c757ce0ee..4d292a016ca0 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -28,6 +28,7 @@
> #include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_dmc.h"
>+#include "intel_dmc_regs.h"
>
> /**
>  * DOC: DMC Firmware Support
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
>new file mode 100644
>index 000000000000..e436fe93a2da
>--- /dev/null
>+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
>@@ -0,0 +1,31 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2022 Intel Corporation
>+ */
>+
>+#ifndef __INTEL_DMC_REGS_H__
>+#define __INTEL_DMC_REGS_H__
>+
>+#include "i915_reg_defs.h"
>+
>+#define DMC_PROGRAM(addr, i)	_MMIO((addr) + (i) * 4)
>+#define DMC_SSP_BASE_ADDR_GEN9	0x00002FC0
>+#define DMC_HTP_ADDR_SKL	0x00500034
>+#define DMC_SSP_BASE		_MMIO(0x8F074)
>+#define DMC_HTP_SKL		_MMIO(0x8F004)
>+#define DMC_LAST_WRITE		_MMIO(0x8F034)
>+#define DMC_LAST_WRITE_VALUE	0xc003b400
>+/* MMIO address range for DMC program (0x80000 - 0x82FFF) */

this comment seems outdated. Or at least unneeded

Anyway:

Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi

>+#define DMC_MMIO_START_RANGE	0x80000
>+#define DMC_MMIO_END_RANGE	0x8FFFF
>+#define SKL_DMC_DC3_DC5_COUNT	_MMIO(0x80030)
>+#define SKL_DMC_DC5_DC6_COUNT	_MMIO(0x8002C)
>+#define BXT_DMC_DC3_DC5_COUNT	_MMIO(0x80038)
>+#define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
>+#define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
>+#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
>+
>+#define TGL_DMC_DEBUG3		_MMIO(0x101090)
>+#define DG1_DMC_DEBUG3		_MMIO(0x13415c)
>+
>+#endif /* __INTEL_DMC_REGS_H__ */