[Intel-gfx] [PATCH v5 13/19] drm/i915: Introduce new Tile 4 format

[Chery, Nanley G]

Hi all,

Found an error in this description..

> From: Stanislav Lisovskiy stanislav.lisovskiy at intel.com<mailto:stanislav.lisovskiy at intel.com>
>
> This tiling layout uses 4KB tiles in a row-major layout. It has the same
> shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
> only differs from Tile Y at the 256B granularity in between. At this
> granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
> of 64B x 8 rows.
>

256B should be 512B (same feedback for the modifier description).

Regards,
Nanley

> Reviewed-by: Imre Deak imre.deak at intel.com<mailto:imre.deak at intel.com>
> Acked-by: Nanley Chery nanley.g.chery at intel.com<mailto:nanley.g.chery at intel.com>
> Signed-off-by: Stanislav Lisovskiy stanislav.lisovskiy at intel.com<mailto:stanislav.lisovskiy at intel.com>
> ---
>  include/uapi/drm/drm_fourcc.h | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index fc0c1454d275..b73fe6797fc3 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -572,6 +572,17 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
>
> +/*
> + * Intel Tile 4 layout
> + *
> + * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
> + * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
> + * only differs from Tile Y at the 256B granularity in between. At this
> + * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
> + * of 64B x 8 rows.
> + */
> +#define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>   *
>
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