[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations

[Patchwork]

== Series Details ==

Series: drm/i915: Start reordering modeset clock calculations
URL   : https://patchwork.freedesktop.org/series/101789/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
3b931b51817a drm/i915: Make .get_dplls() return int
1b2d4a4a599e drm/i915: Pass dev_priv to intel_shared_dpll_init()
33ae484eb053 drm/i915: Remove pointless dpll_funcs checks
4a49b686c648 drm/i915: Adjust .crtc_compute_clock() calling convention
2e1ac19c4047 drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
4e89276790b2 drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
3f11772ea836 drm/i915: Clear the dpll_hw_state when disabling a pipe
ca60dc3a2f8a drm/i915: Split out dg2_crtc_compute_clock()
f71777efae30 drm/i915: Add crtc .crtc_get_shared_dpll()
c64fe9a7ba0c drm/i915: Split shared dpll .get_dplls() into compute and get phases
-:191: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#191: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063:
+		SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;

total: 0 errors, 0 warnings, 1 checks, 516 lines checked
f78032f898c7 drm/i915: Do .crtc_compute_clock() earlier
4d0d47819c90 drm/i915: Clean up DPLL related debugs
5d0098769f10 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()