[Intel-gfx] [PATCH] drm/i915/adlp: Fix register corruption after DDI clock enabling

[Ville Syrjälä]

On Wed, Mar 23, 2022 at 10:17:49PM +0200, Imre Deak wrote:
> Accessing the DDI_BUF_CTL register without the port's DDI clock being
> enabled (to set/clear the TypeC PHY ownership for the port) can lead to
> a corrupted value read during any i915 register access right after the
> DDI clock is enabled.
> 
> The root cause is the way clock synchronization works for this register,
> controlled by the CHICKEN_DCPR_1 DDI_CLOCK_REG_ACCESS flag. Correctly
> this flag should be cleared on ADLP (see the Bspec link below), however
> after bootup the flag is set.
> 
> One easily reproducible issue is an unclaimed register access of the
> PWR_WELL_CTL_DDI2 register, programmed right after DDI clock enabling to
> enable the port's DDI_IO power well (see the HSDES, VLK links below).
> With the correct setting above this problem can't be reproduced.
> 
> Bspec: 49189
> HSDES: 18019028154
> VLK: 28328, 28655
> 
> Cc: Jouni Högander <jouni.hogander at intel.com>
> Cc: Arthur J Runyan <arthur.j.runyan at intel.com>
> Signed-off-by: Imre Deak <imre.deak at intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>  drivers/gpu/drm/i915/intel_pm.c | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a0d652f19ff93..d83bd7a75c788 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5939,6 +5939,7 @@
>  #define   ICL_DELAY_PMRSP			REG_BIT(22)
>  #define   DISABLE_FLR_SRC			REG_BIT(15)
>  #define   MASK_WAKEMEM				REG_BIT(13)
> +#define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
>  
>  #define GEN11_CHICKEN_DCPR_2			_MMIO(0x46434)
>  #define   DCPR_MASK_MAXLATENCY_MEMUP_CLR	REG_BIT(27)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2c3cd4d775daf..4291963013c51 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7470,6 +7470,9 @@ static void adlp_init_clock_gating(struct drm_i915_private *dev_priv)
>  
>  	/* Wa_22011091694:adlp */
>  	intel_de_rmw(dev_priv, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
> +
> +	/* Bspec/49189 Initialize Sequence */
> +	intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
>  }
>  
>  static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
> -- 
> 2.30.2

-- 
Ville Syrjälä
Intel