[Intel-gfx] [PATCH v5 6/9] drm/i915/gt: offset handling for multiple copy engines

[Ramalingam C]

On 2022-03-24 at 17:20:28 +0100, Thomas Hellström (Intel) wrote:
> 
> On 3/21/22 23:44, Ramalingam C wrote:
> > Handle the src and dst chunk offsets for different instances of the copy
> > engines.
> > 
> > Signed-off-by: Ramalingam C <ramalingam.c at intel.com>
> > ---
> >   drivers/gpu/drm/i915/gt/intel_migrate.c | 3 +++
> >   1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> > index 39a5f8ae664d..5f6341f91622 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> > @@ -614,6 +614,9 @@ static int emit_copy(struct i915_request *rq,
> >   	u32 instance = rq->engine->instance;
> >   	u32 *cs;
> > +	src_offset += (u64)rq->engine->instance << 32;
> > +	dst_offset += (u64)rq->engine->instance << 32;
> > +
> 
> Again, these are nops since the offsets are 32-bit.
> 
> Also the instance selection is already handled in the functon, so I think
> this patch can be dropped.

Thanks. Dropped this patch. and made copy and clear uniform with respect to
engine index handling for offset.

Ram.
> 
> 
> >   	cs = intel_ring_begin(rq, ver >= 8 ? 10 : 6);
> >   	if (IS_ERR(cs))
> >   		return PTR_ERR(cs);