[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Start reordering modeset clock calculations (rev2)
URL   : https://patchwork.freedesktop.org/series/101789/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
0cc647463e24 drm/i915: Make .get_dplls() return int
26c2cde200f7 drm/i915: Pass dev_priv to intel_shared_dpll_init()
9cf895d61032 drm/i915: Remove pointless dpll_funcs checks
b7d2de662b35 drm/i915: Adjust .crtc_compute_clock() calling convention
9c981811d68a drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
b0721bb72949 drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
9ecae4f49f80 drm/i915: Clear the dpll_hw_state when disabling a pipe
beebcc4f0775 drm/i915: Split out dg2_crtc_compute_clock()
c5be89e9a6f5 drm/i915: Add crtc .crtc_get_shared_dpll()
0ae7daafcb24 drm/i915: Split shared dpll .get_dplls() into compute and get phases
-:191: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#191: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063:
+		SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;

total: 0 errors, 0 warnings, 1 checks, 516 lines checked
6bcc7005f5e4 drm/i915: Do .crtc_compute_clock() earlier
1d25064542ce drm/i915: Clean up DPLL related debugs
1ebfaa21192e drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()