[Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

[Ville Syrjälä]

On Tue, Mar 29, 2022 at 03:30:59PM -0700, José Roberto de Souza wrote:
> MBUS_DBOX_B2B_TRANSACTIONS_MAX, MBUS_DBOX_B2B_TRANSACTIONS_DELAY and
> MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN were being programmed with
> zeros while specification has different default values for this
> registers in display 12 and newer.
> 
> While at it also converting all MBUS_DBOX macros to use REG_* macros.
> 
> BSpec: 50343
> BSpec: 20231
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++---
>  drivers/gpu/drm/i915/i915_reg.h              | 26 ++++++++++++--------
>  2 files changed, 26 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 28bfb73ae6471..234f363aad651 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1829,13 +1829,20 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
> -	u32 val;
> +	u32 val = 0;
> +
> +	if (DISPLAY_VER(dev_priv) >= 12) {
> +		val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
> +		val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
> +		val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
> +	}
>  
>  	/* Wa_22010947358:adl-p */
>  	if (IS_ALDERLAKE_P(dev_priv))
> -		val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4);
> +		val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
> +				     MBUS_DBOX_A_CREDIT(4);
>  	else
> -		val = MBUS_DBOX_A_CREDIT(2);
> +		val |= MBUS_DBOX_A_CREDIT(2);

It might make sense to have per-platform functions to determine
the whole register value. But that's a separate topic.

>  
>  	if (DISPLAY_VER(dev_priv) >= 12) {
>  		val |= MBUS_DBOX_BW_CREDIT(2);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a0d652f19ff93..f47f9dfc9b0ce 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1103,16 +1103,22 @@
>  #define MBUS_ABOX_BT_CREDIT_POOL1_MASK	(0x1F << 0)
>  #define MBUS_ABOX_BT_CREDIT_POOL1(x)	((x) << 0)
>  
> -#define _PIPEA_MBUS_DBOX_CTL		0x7003C
> -#define _PIPEB_MBUS_DBOX_CTL		0x7103C
> -#define PIPE_MBUS_DBOX_CTL(pipe)	_MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
> -						   _PIPEB_MBUS_DBOX_CTL)
> -#define MBUS_DBOX_BW_CREDIT_MASK	(3 << 14)
> -#define MBUS_DBOX_BW_CREDIT(x)		((x) << 14)
> -#define MBUS_DBOX_B_CREDIT_MASK		(0x1F << 8)
> -#define MBUS_DBOX_B_CREDIT(x)		((x) << 8)
> -#define MBUS_DBOX_A_CREDIT_MASK		(0xF << 0)
> -#define MBUS_DBOX_A_CREDIT(x)		((x) << 0)
> +#define _PIPEA_MBUS_DBOX_CTL			0x7003C
> +#define _PIPEB_MBUS_DBOX_CTL			0x7103C
> +#define PIPE_MBUS_DBOX_CTL(pipe)		_MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
> +							   _PIPEB_MBUS_DBOX_CTL)
> +#define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK	REG_GENMASK(24, 20)

Could throw in some tgl+ comments onto these b2b defines.

> +#define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x)	REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x)
> +#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK	REG_GENMASK(19, 17)
> +#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x)	REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x)
> +#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK	REG_GENMASK(19, 17)

Second MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK define.

with that removed:
Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> +#define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN	REG_BIT(16)
> +#define MBUS_DBOX_BW_CREDIT_MASK		REG_GENMASK(15, 14)
> +#define MBUS_DBOX_BW_CREDIT(x)			REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)
> +#define MBUS_DBOX_B_CREDIT_MASK			REG_GENMASK(12, 8)
> +#define MBUS_DBOX_B_CREDIT(x)			REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)
> +#define MBUS_DBOX_A_CREDIT_MASK			REG_GENMASK(3, 0)
> +#define MBUS_DBOX_A_CREDIT(x)			REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)
>  
>  #define MBUS_UBOX_CTL			_MMIO(0x4503C)
>  #define MBUS_BBOX_CTL_S1		_MMIO(0x45040)
> -- 
> 2.35.1

-- 
Ville Syrjälä
Intel