[Intel-gfx] [PATCH 05/12] drm/i915: Drop has_rc6p from device info

[Matt Roper]

On Wed, May 04, 2022 at 12:07:49PM -0700, José Roberto de Souza wrote:
> No need to have this parameter in intel_device_info struct
> as it was only supported in graphics version 6 and 7 not including
> haswell.
> 
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
>  drivers/gpu/drm/i915/i915_pci.c          | 3 ---
>  drivers/gpu/drm/i915/intel_device_info.h | 1 -
>  3 files changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d29dca83185ac..602e056edd314 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1310,7 +1310,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  
>  /* ilk does support rc6, but we do not implement [power] contexts */
>  #define HAS_RC6(dev_priv)		 (GRAPHICS_VER(dev_priv) >= 6)
> -#define HAS_RC6p(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6p)
> +#define HAS_RC6p(dev_priv)		 (GRAPHICS_VER(dev_priv) >= 6 && \
> +					  GRAPHICS_VER(dev_priv) <= 7 && \

BTW, I just remembered that we can write simple ranges like this (where
the release number doesn't matter) as:

        IS_GRAPHICS_VER(i915, 6, 7)

so you might want to use that to simplify here and in some of the other
patches.

Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>


> +					  !IS_HASWELL(dev_priv))
>  #define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */
>  
>  #define HAS_RPS(dev_priv)	(INTEL_INFO(dev_priv)->has_rps)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 90584c462f225..516f28d4db611 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -405,7 +405,6 @@ static const struct intel_device_info ilk_m_info = {
>  	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>  	.has_coherent_ggtt = true, \
>  	.has_llc = 1, \
> -	.has_rc6p = 1, \
>  	.has_rps = true, \
>  	.dma_mask_size = 40, \
>  	.ppgtt_type = INTEL_PPGTT_ALIASING, \
> @@ -455,7 +454,6 @@ static const struct intel_device_info snb_m_gt2_info = {
>  	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>  	.has_coherent_ggtt = true, \
>  	.has_llc = 1, \
> -	.has_rc6p = 1, \
>  	.has_reset_engine = true, \
>  	.has_rps = true, \
>  	.dma_mask_size = 40, \
> @@ -540,7 +538,6 @@ static const struct intel_device_info vlv_info = {
>  	.display.has_ddi = 1, \
>  	.display.has_fpga_dbg = 1, \
>  	.display.has_dp_mst = 1, \
> -	.has_rc6p = 0 /* RC6p removed-by HSW */, \
>  	HSW_PIPE_OFFSETS, \
>  	.has_runtime_pm = 1
>  
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index b3244170c4638..599cb265946b8 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -156,7 +156,6 @@ enum intel_ppgtt_type {
>  	func(has_mslices); \
>  	func(has_pooled_eu); \
>  	func(has_pxp); \
> -	func(has_rc6p); \
>  	func(has_rps); \
>  	func(has_runtime_pm); \
>  	func(has_snoop); \
> -- 
> 2.36.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795