[Intel-gfx] [PATCH 09/12] drm/i915: Drop has_dp_mst from device info

[Matt Roper]

On Wed, May 04, 2022 at 12:07:53PM -0700, José Roberto de Souza wrote:
> No need to have this parameter in intel_device_info struct
> as the requirement to support it is the DDI support.
> 
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h          | 2 +-
>  drivers/gpu/drm/i915/i915_pci.c          | 3 ---
>  drivers/gpu/drm/i915/intel_device_info.h | 1 -
>  3 files changed, 1 insertion(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a354815445238..6b8a4e6649d9b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1295,13 +1295,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  
>  #define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
>  
> -#define HAS_DP_MST(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dp_mst)
>  #define HAS_DP20(dev_priv)	(IS_DG2(dev_priv))
>  
>  #define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
>  #define HAS_DDI(dev_priv)		 (DISPLAY_VER(dev_priv) >= 9 || \
>  					  IS_HASWELL(dev_priv) || \
>  					  IS_BROADWELL(dev_priv))
> +#define HAS_DP_MST(dev_priv)		 (HAS_DDI(dev_priv))
>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
>  #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
>  #define HAS_PSR_HW_TRACKING(dev_priv) \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 96270c0ddf06c..d8b5e972109f9 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -534,7 +534,6 @@ static const struct intel_device_info vlv_info = {
>  	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
>  		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
>  	.display.has_fpga_dbg = 1, \
> -	.display.has_dp_mst = 1, \
>  	HSW_PIPE_OFFSETS, \
>  	.has_runtime_pm = 1
>  
> @@ -686,7 +685,6 @@ static const struct intel_device_info skl_gt4_info = {
>  	.has_runtime_pm = 1, \
>  	.display.has_dmc = 1, \
>  	.has_rps = true, \
> -	.display.has_dp_mst = 1, \
>  	.has_logical_ring_contexts = 1, \
>  	.dma_mask_size = 39, \
>  	.ppgtt_type = INTEL_PPGTT_FULL, \
> @@ -925,7 +923,6 @@ static const struct intel_device_info adl_s_info = {
>  	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
>  		BIT(DBUF_S4),							\
>  	.display.has_dmc = 1,							\
> -	.display.has_dp_mst = 1,						\
>  	.display.has_dsc = 1,							\
>  	.display.fbc_mask = BIT(INTEL_FBC_A),					\
>  	.display.has_fpga_dbg = 1,						\
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index d809d44098c63..c4e85976d8948 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -166,7 +166,6 @@ enum intel_ppgtt_type {
>  	func(cursor_needs_physical); \
>  	func(has_cdclk_crawl); \
>  	func(has_dmc); \
> -	func(has_dp_mst); \
>  	func(has_dsc); \
>  	func(has_fpga_dbg); \
>  	func(has_gmch); \
> -- 
> 2.36.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795