[Intel-gfx] [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config

[Matt Roper]

On Thu, May 05, 2022 at 12:02:45PM +0100, Tvrtko Ursulin wrote:
> 
> On 04/05/2022 19:17, Matt Roper wrote:
> > On Wed, May 04, 2022 at 06:59:32PM +0100, Tvrtko Ursulin wrote:
> > > 
> > > On 04/05/2022 17:48, Matt Roper wrote:
> > > > On Wed, May 04, 2022 at 01:07:14PM +0100, Tvrtko Ursulin wrote:
> > > > > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> > > > > 
> > > > > DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
> > > > > to exercise a certain code path, so in case of values coming from MMIO
> > > > > reads we cannot be sure CI will have all the possible SKUs and parts.
> > > > > 
> > > > > Use drm_warn instead and move logging to init phase while at it.
> > > > 
> > > > Changing to drm_warn looks good, although moving the location changes
> > > > the intent a bit; I think originally the idea was to warn if we were
> > > > trying to do a steering lookup for a type that we never initialized
> > > > (e.g., an LNCF lookup for a !HAS_MSLICES platform where we never even
> > > > read the register in the first place).  But I don't think we've ever
> > > > made a mistake that would cause us to trip the warning, so it probably
> > > > isn't terribly important to keep it there.
> > > 
> > > Ah I see.. there we could put something like:
> > > 
> > > 	case MSLICE:
> > > 		GEM_WARN_ON(!HAS_MSLICES(...));
> > > 
> > 
> > Yeah, that would work for MSLICE and LNCF.  Although L3BANK is a bit
> > stranger since we have multiple platforms that obtain the L3 bank mask
> > in completely different ways (Xe_HP reads it from XEHP_FUSE4, whereas
> > gen11/gen12 reads it from GEN10_MIRROR_FUSE3).  We want to make sure
> > there that no matter which branch of init we take, we didn't forget to
> > initialize l3bank_mask somehow.
> 
> The two init paths are not something present in drm-tip at this point,
> right? At least I couldn't find it. In which case it could be handled later
> by moving the drm_warn to tail of intel_gt_init_mmio, give or take.

Oh, you're right.  The new fuse register actually shows up on a future
platform rather than Xe_HP so the two init paths aren't present yet.

> 
> Anyway, I've sent v2 out with your r-b and GEM_WARN_ON for mslice/lncf. I
> won't merge it though until you definitely are okay with it so please have a
> look and confirm.

Yeah, v2 looks fine.  Thanks.


Matt

> 
> Regards,
> 
> Tvrtko
> 
> 
> > 
> > Matt
> > 
> > > ?
> > > 
> > > Regards,
> > > 
> > > Tvrtko
> > > 
> > > > 
> > > > Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
> > > > 
> > > > > 
> > > > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> > > > > Cc: Matt Roper <matthew.d.roper at intel.com>
> > > > > Cc: Jani Nikula <jani.nikula at intel.com>
> > > > > ---
> > > > >    drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++++++-------
> > > > >    1 file changed, 6 insertions(+), 7 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > > index 53307ca0eed0..c474e5c3ea5e 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > > @@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> > > > >    	 * An mslice is unavailable only if both the meml3 for the slice is
> > > > >    	 * disabled *and* all of the DSS in the slice (quadrant) are disabled.
> > > > >    	 */
> > > > > -	if (HAS_MSLICES(i915))
> > > > > +	if (HAS_MSLICES(i915)) {
> > > > >    		gt->info.mslice_mask =
> > > > >    			slicemask(gt, GEN_DSS_PER_MSLICE) |
> > > > >    			(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> > > > >    			 GEN12_MEML3_EN_MASK);
> > > > > +		if (!gt->info.mslice_mask) /* should be impossible! */
> > > > > +			drm_warn(&i915->drm, "mslice mask all zero!\n");
> > > > > +	}
> > > > >    	if (IS_DG2(i915)) {
> > > > >    		gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
> > > > > @@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> > > > >    		gt->info.l3bank_mask =
> > > > >    			~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> > > > >    			GEN10_L3BANK_MASK;
> > > > > +		if (!gt->info.l3bank_mask) /* should be impossible! */
> > > > > +			drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
> > > > >    	} else if (HAS_MSLICES(i915)) {
> > > > >    		MISSING_CASE(INTEL_INFO(i915)->platform);
> > > > >    	}
> > > > > @@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
> > > > >    {
> > > > >    	switch (type) {
> > > > >    	case L3BANK:
> > > > > -		GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
> > > > > -
> > > > >    		*sliceid = 0;		/* unused */
> > > > >    		*subsliceid = __ffs(gt->info.l3bank_mask);
> > > > >    		break;
> > > > >    	case MSLICE:
> > > > > -		GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
> > > > > -
> > > > >    		*sliceid = __ffs(gt->info.mslice_mask);
> > > > >    		*subsliceid = 0;	/* unused */
> > > > >    		break;
> > > > >    	case LNCF:
> > > > > -		GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
> > > > > -
> > > > >    		/*
> > > > >    		 * An LNCF is always present if its mslice is present, so we
> > > > >    		 * can safely just steer to LNCF 0 in all cases.
> > > > > -- 
> > > > > 2.32.0
> > > > > 
> > > > 
> > 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795