[Intel-gfx] [PATCH 23/26] drm/i915: Require an exact DP link freq match for the DG2 PLL

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> No idea why the DG2 PLL DP link frequency calculation is allowing
> a non-exact match. That makes no sense so get rid of it.

Cc: Matt.

This also makes the hdmi link rate check in the same function redundant.

Reviewed-by: Jani Nikula <jani.nikula at intel.com>


>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index 0dd4775e8195..877f9a4bd7a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -597,7 +597,7 @@ int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
>  		return -EINVAL;
>  
>  	for (i = 0; tables[i]; i++) {
> -		if (crtc_state->port_clock <= tables[i]->clock) {
> +		if (crtc_state->port_clock == tables[i]->clock) {
>  			crtc_state->mpllb_state = *tables[i];
>  			return 0;
>  		}

-- 
Jani Nikula, Intel Open Source Graphics Center