[Intel-gfx] [PATCH v3] drm/i915/dg2: Support 4k at 30 on HDMI

[Matt Roper]

On Wed, May 25, 2022 at 01:34:01PM +0530, Ankit Nautiyal wrote:
> From: Vandita Kulkarni <vandita.kulkarni at intel.com>
> 
> This patch adds a fix to support 297MHz of dot clock by calculating
> the pll values using synopsis algorithm.
> This will help to support 4k at 30 mode for HDMI monitors on DG2.
> 
> v2: As per the algorithm, set MPLLB VCO range control bits to 3,
> in register SNPS_PHY_MPLLB_DIV for 297Mhz. (Matt)
> 
> v3: Fix typo. (Ankit)
> 
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni at intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

and applied to drm-intel-next.  Thanks for the patch.

> ---
>  drivers/gpu/drm/i915/display/intel_snps_phy.c | 32 +++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index 0dd4775e8195..cc1270978b67 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -517,6 +517,37 @@ static const struct intel_mpllb_state dg2_hdmi_148_5 = {
>  		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
>  };
>  
> +/* values in the below table are calculted using the algo */
> +static const struct intel_mpllb_state dg2_hdmi_297 = {
> +	.clock = 297000,
> +	.ref_control =
> +		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
> +	.mpllb_cp =
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
> +	.mpllb_div =
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
> +	.mpllb_div2 =
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
> +	.mpllb_fracn1 =
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
> +	.mpllb_fracn2 =
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
> +	.mpllb_sscen =
> +		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
> +};
> +
>  static const struct intel_mpllb_state dg2_hdmi_594 = {
>  	.clock = 594000,
>  	.ref_control =
> @@ -551,6 +582,7 @@ static const struct intel_mpllb_state * const dg2_hdmi_tables[] = {
>  	&dg2_hdmi_27_0,
>  	&dg2_hdmi_74_25,
>  	&dg2_hdmi_148_5,
> +	&dg2_hdmi_297,
>  	&dg2_hdmi_594,
>  	NULL,
>  };
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation