[Intel-gfx] [PATCH] drm/i915/psr: Remove inappropriate DSC slice alignment warning

[Souza, Jose]

On Fri, 2022-10-21 at 08:49 +0300, Jouni Högander wrote:
> Selective update area is now aligned with DSC slice height when
> DSC is enabled. Remove inappropriate warning about missing DSC
> alignment.
> 
> Cc: José Roberto de Souza <jose.souza at intel.com>
> Cc: Mika Kahola <mika.kahola at intel.com>
> 
> Fixes: 47d4ae2192cb ("drm/i915/mtl: Extend PSR support")
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7212
> Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 904a1049eff3..64e9e134fdca 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1678,9 +1678,6 @@ static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *c
>  	pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
>  	if (pipe_clip->y2 % y_alignment)
>  		pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
> -
> -	if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
> -		drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");

It is necessary check if DSC alignment and PSR2 alignment matches, if not PSR2 can't be enabled.

>  }
>  
>  /*