[Intel-gfx] [PATCH v2 04/18] drm/i915: Clean up chv CGM (de)gamma defines

[Jani Nikula]

On Thu, 10 Nov 2022, Ville Syrjala <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Add the missing ldw vs. udw information to the CGM (de)gamma
> bit definitions to make it a bit easier to see which should
> be used where.
>
> Also use the these appropriately in the LUT entry pack/unpack
> functions.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 18 +++++++++---------
>  drivers/gpu/drm/i915/i915_reg.h            | 16 ++++++++++------
>  2 files changed, 19 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 758869971e45..8e92eb61abac 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1077,13 +1077,13 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
>  
>  static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
>  {
> -	return drm_color_lut_extract(color->green, 14) << 16 |
> -		drm_color_lut_extract(color->blue, 14);
> +	return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK, drm_color_lut_extract(color->green, 14)) |
> +		REG_FIELD_PREP(CGM_PIPE_DEGAMMA_BLUE_LDW_MASK, drm_color_lut_extract(color->blue, 14));
>  }
>  
>  static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
>  {
> -	return drm_color_lut_extract(color->red, 14);
> +	return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_RED_UDW_MASK, drm_color_lut_extract(color->red, 14));
>  }
>  
>  static void chv_load_cgm_degamma(struct intel_crtc *crtc,
> @@ -1104,20 +1104,20 @@ static void chv_load_cgm_degamma(struct intel_crtc *crtc,
>  
>  static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color)
>  {
> -	return drm_color_lut_extract(color->green, 10) << 16 |
> -		drm_color_lut_extract(color->blue, 10);
> +	return REG_FIELD_PREP(CGM_PIPE_GAMMA_GREEN_LDW_MASK, drm_color_lut_extract(color->green, 10)) |
> +		REG_FIELD_PREP(CGM_PIPE_GAMMA_BLUE_LDW_MASK, drm_color_lut_extract(color->blue, 10));
>  }
>  
>  static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color)
>  {
> -	return drm_color_lut_extract(color->red, 10);
> +	return REG_FIELD_PREP(CGM_PIPE_GAMMA_RED_UDW_MASK, drm_color_lut_extract(color->red, 10));
>  }
>  
>  static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
>  {
> -	entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10);
> -	entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10);
> -	entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10);
> +	entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_LDW_MASK, ldw), 10);
> +	entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_LDW_MASK, ldw), 10);
> +	entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_UDW_MASK, udw), 10);
>  }
>  
>  static void chv_load_cgm_gamma(struct intel_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ecb34f133980..f4c08509e629 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7725,13 +7725,17 @@ enum skl_power_gate {
>  #define _CGM_PIPE_A_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6790C)
>  #define _CGM_PIPE_A_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x67910)
>  #define _CGM_PIPE_A_DEGAMMA	(VLV_DISPLAY_BASE + 0x66000)
> -#define   CGM_PIPE_DEGAMMA_RED_MASK	REG_GENMASK(13, 0)
> -#define   CGM_PIPE_DEGAMMA_GREEN_MASK	REG_GENMASK(29, 16)
> -#define   CGM_PIPE_DEGAMMA_BLUE_MASK	REG_GENMASK(13, 0)
> +/* cgm degamma ldw */
> +#define   CGM_PIPE_DEGAMMA_GREEN_LDW_MASK	REG_GENMASK(29, 16)
> +#define   CGM_PIPE_DEGAMMA_BLUE_LDW_MASK	REG_GENMASK(13, 0)
> +/* cgm degamma udw */
> +#define   CGM_PIPE_DEGAMMA_RED_UDW_MASK		REG_GENMASK(13, 0)
>  #define _CGM_PIPE_A_GAMMA	(VLV_DISPLAY_BASE + 0x67000)
> -#define   CGM_PIPE_GAMMA_RED_MASK	REG_GENMASK(9, 0)
> -#define   CGM_PIPE_GAMMA_GREEN_MASK	REG_GENMASK(25, 16)
> -#define   CGM_PIPE_GAMMA_BLUE_MASK	REG_GENMASK(9, 0)
> +/* cgm gamma ldw */
> +#define   CGM_PIPE_GAMMA_GREEN_LDW_MASK		REG_GENMASK(25, 16)
> +#define   CGM_PIPE_GAMMA_BLUE_LDW_MASK		REG_GENMASK(9, 0)
> +/* cgm gamma udw */
> +#define   CGM_PIPE_GAMMA_RED_UDW_MASK		REG_GENMASK(9, 0)
>  #define _CGM_PIPE_A_MODE	(VLV_DISPLAY_BASE + 0x67A00)
>  #define   CGM_PIPE_MODE_GAMMA	(1 << 2)
>  #define   CGM_PIPE_MODE_CSC	(1 << 1)

-- 
Jani Nikula, Intel Open Source Graphics Center