[Intel-gfx] [PATCH 1/2] drm/ttm: Clean up page shift operation
Christian König
christian.koenig at amd.com
Wed Nov 16 12:25:39 UTC 2022
Am 16.11.22 um 09:50 schrieb Somalapuram Amaranath:
> remove page shift operations as ttm_resource moved
> from num_pages to size_t size in bytes.
>
> Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 +---
> drivers/gpu/drm/ttm/ttm_range_manager.c | 2 +-
> 2 files changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 974e85d8b6cc..19ad365dc159 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -541,12 +541,10 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
> if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
> /* GWS and OA don't need any alignment. */
> page_align = bp->byte_align;
> - size <<= PAGE_SHIFT;
> -
> } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
> /* Both size and alignment must be a multiple of 4. */
> page_align = ALIGN(bp->byte_align, 4);
> - size = ALIGN(size, 4) << PAGE_SHIFT;
> + size = ALIGN(size, 4);
> } else {
> /* Memory should be aligned at least to a page size. */
> page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
> diff --git a/drivers/gpu/drm/ttm/ttm_range_manager.c b/drivers/gpu/drm/ttm/ttm_range_manager.c
> index 0a8bc0b7f380..4c7cba4ffdbf 100644
> --- a/drivers/gpu/drm/ttm/ttm_range_manager.c
> +++ b/drivers/gpu/drm/ttm/ttm_range_manager.c
> @@ -83,7 +83,7 @@ static int ttm_range_man_alloc(struct ttm_resource_manager *man,
>
> spin_lock(&rman->lock);
> ret = drm_mm_insert_node_in_range(mm, &node->mm_nodes[0],
> - PFN_UP(node->base.size),
> + node->base.size,
> bo->page_alignment, 0,
> place->fpfn, lpfn, mode);
You need to make sure that fpfn and lpfn are now page shifted instead.
Same for the overlap and compatible functions.
Regards,
Christian.
> spin_unlock(&rman->lock);
More information about the Intel-gfx
mailing list