[Intel-gfx] [PATCH 06/10] drm/i915/dvo: Rename the "active data order" bits

[Jani Nikula]

On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> We have two sets of bits for DVO "data order" stuff. Rename
> one set to ACT_DATA_ORDER to make it clear they are separate
> bitfields.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dvo.c | 4 ++--
>  drivers/gpu/drm/i915/i915_reg.h          | 8 ++++----
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index 255deb55b932..b36c3a620250 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -288,10 +288,10 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
>  	enum pipe pipe = crtc->pipe;
>  	u32 dvo_val;
>  
> -	/* Save the data order, since I don't know what it should be set to. */
> +	/* Save the active data order, since I don't know what it should be set to. */
>  	dvo_val = intel_de_read(i915, DVO(port)) &
>  		  (DVO_DEDICATED_INT_ENABLE |
> -		   DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
> +		   DVO_PRESERVE_MASK | DVO_ACT_DATA_ORDER_GBRG);
>  	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
>  		   DVO_BLANK_ACTIVE_HIGH;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 89c834d8fff8..464be86d6125 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2600,10 +2600,10 @@
>  #define   DVO_VSYNC_TRISTATE		(1 << 9)
>  #define   DVO_HSYNC_TRISTATE		(1 << 8)
>  #define   DVO_BORDER_ENABLE		(1 << 7)
> -#define   DVO_DATA_ORDER_GBRG		(1 << 6)
> -#define   DVO_DATA_ORDER_RGGB		(0 << 6)
> -#define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
> -#define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
> +#define   DVO_ACT_DATA_ORDER_GBRG		(1 << 6)
> +#define   DVO_ACT_DATA_ORDER_RGGB		(0 << 6)
> +#define   DVO_ACT_DATA_ORDER_GBRG_ERRATA	(0 << 6)
> +#define   DVO_ACT_DATA_ORDER_RGGB_ERRATA	(1 << 6)
>  #define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
>  #define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
>  #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)

-- 
Jani Nikula, Intel Open Source Graphics Center