[Intel-gfx] [PATCH 0/1] Implement workaround for PLL enabling for DG2/MTL

[Stanislav Lisovskiy]

It has been noticed by HW team, that there are might be problems
when PLL is being enabled with CDCLK squashing being turned on,
which might result in loosing register access and/or FIFO underrun.
As a workaround it has been proposed to disable CDCLK squashing right
before PLL is enabled and enable squashing later, if needed.

Stanislav Lisovskiy (1):
  drm/i915: Implement workaround for CDCLK PLL disable/enable

 drivers/gpu/drm/i915/display/intel_cdclk.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

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2.37.3