[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Explicit MCR handling and MTL steering (rev2)

[Patchwork]

== Series Details ==

Series: Explicit MCR handling and MTL steering (rev2)
URL   : https://patchwork.freedesktop.org/series/108755/
State : warning

== Summary ==

Error: dim checkpatch failed
bf9edd88aea6 drm/i915/gen8: Create separate reg definitions for new MCR registers
-:292: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#292: FILE: drivers/gpu/drm/i915/intel_pm.c:4343:
+	intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl & ~GEN8_DOP_CLOCK_GATE_ENABLE);

-:311: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#311: FILE: drivers/gpu/drm/i915/intel_pm.c:4517:
+	intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL) &

total: 0 errors, 2 warnings, 0 checks, 223 lines checked
0fc47efe5eb9 drm/i915/xehp: Create separate reg definitions for new MCR registers
c3383e4218c1 drm/i915/gt: Drop a few unused register definitions
d41aca1d73e0 drm/i915/gt: Correct prefix on a few registers
0da9a749484d drm/i915/gt: Add intel_gt_mcr_multicast_rmw() operation
7f4fc3c493ef drm/i915/xehp: Check for faults on primary GAM
2af2f36fab78 drm/i915/gt: Add intel_gt_mcr_wait_for_reg_fw()
a01a5757e7d7 drm/i915: Define MCR registers explicitly
-:149: WARNING:LONG_LINE_COMMENT: line length of 102 exceeds 100 columns
#149: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:948:
+#define XEHP_LNCFCMOCS(i)			MCR_REG(0xb020 + (i) * 4)	/* L3 Cache Control */

total: 0 errors, 1 warnings, 0 checks, 351 lines checked
01a8cd41ae1b drm/i915/gt: Always use MCR functions on multicast registers
bedd7ad259b9 drm/i915/guc: Handle save/restore of MCR registers explicitly
0c36060edf2c drm/i915/gt: Add MCR-specific workaround initializers
-:119: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#119: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:297:
+	wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
 		     PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);

-:631: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#631: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:2255:
+		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
 			     GEN12_DISABLE_READ_SUPPRESSION);

-:650: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#650: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:2271:
+		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
 			     MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE);

-:714: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#714: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:2323:
+			   0 /* Wa_14012342262 :write-only reg, so skip
+				verification */,

total: 0 errors, 1 warnings, 3 checks, 899 lines checked
d8c8cc59fd59 drm/i915: Define multicast registers as a new type
-:704: WARNING:NEW_TYPEDEFS: do not add new typedefs
#704: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:107:
+typedef struct {

total: 0 errors, 1 warnings, 0 checks, 636 lines checked
d8d24aeb0f55 drm/i915/mtl: Add multicast steering for render GT
-:99: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#99: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:164:
+			gt->info.l3bank_mask |= (0x3 << 2*i);
 			                                 ^

-:127: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#127: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:258:
+		old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);

-:138: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#138: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:267:
+		old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);

total: 0 errors, 0 warnings, 3 checks, 226 lines checked
f82a42d420ed drm/i915/mtl: Add multicast steering for media GT
-:35: CHECK:LINE_SPACING: Please don't use multiple blank lines
#35: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:138:
+
+

total: 0 errors, 0 warnings, 1 checks, 79 lines checked