[Intel-gfx] [PATCH] drm/i915/display: Add DC5 counter and DMC debugfs entries for MTL

[Lucas De Marchi]

On Fri, Oct 07, 2022 at 12:42:03PM -0700, Anusha Srivatsa wrote:
>MTL and dgfx use the same DC5 counter.
>
>While at it, this patch also adds the corresponding
>debugfs entries. Some cleanup wrt dc3co register
>which makes the code more readable.
>
>Driver loads all firmware that it finds in the firmware
>binary but platform doesn't *need* all of them. Cleaning the
>previous debugs entries to reflect which firmware is needed
>and if the needed firmware is loaded or not.
>
>MTL needs both Pipe A and Pipe B DMC to be loaded
>along with Main DMC.
>
>BSpec: 49788
>Cc: Lucas De Marchi <lucas.demarchi at intel.com>
>Cc: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

thanks
Lucas De Marchi

>---
> drivers/gpu/drm/i915/display/intel_dmc.c | 22 ++++++++++------------
> 1 file changed, 10 insertions(+), 12 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index e52ecc0738a6..081a4d0083b1 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -1065,12 +1065,13 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> 	seq_printf(m, "fw loaded: %s\n",
> 		   str_yes_no(intel_dmc_has_payload(i915)));
> 	seq_printf(m, "path: %s\n", dmc->fw_path);
>-	seq_printf(m, "Pipe A fw support: %s\n",
>+	seq_printf(m, "Pipe A fw needed: %s\n",
> 		   str_yes_no(GRAPHICS_VER(i915) >= 12));
> 	seq_printf(m, "Pipe A fw loaded: %s\n",
> 		   str_yes_no(dmc->dmc_info[DMC_FW_PIPEA].payload));
>-	seq_printf(m, "Pipe B fw support: %s\n",
>-		   str_yes_no(IS_ALDERLAKE_P(i915)));
>+	seq_printf(m, "Pipe B fw needed: %s\n",
>+		   str_yes_no(IS_ALDERLAKE_P(i915) ||
>+			      DISPLAY_VER(i915) >= 14));
> 	seq_printf(m, "Pipe B fw loaded: %s\n",
> 		   str_yes_no(dmc->dmc_info[DMC_FW_PIPEB].payload));
>
>@@ -1081,22 +1082,19 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> 		   DMC_VERSION_MINOR(dmc->version));
>
> 	if (DISPLAY_VER(i915) >= 12) {
>-		if (IS_DGFX(i915)) {
>+		i915_reg_t dc3co_reg;
>+
>+		if (IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) {
>+			dc3co_reg = DG1_DMC_DEBUG3;
> 			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> 		} else {
>+			dc3co_reg = TGL_DMC_DEBUG3;
> 			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> 			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> 		}
>
>-		/*
>-		 * NOTE: DMC_DEBUG3 is a general purpose reg.
>-		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
>-		 * reg for DC3CO debugging and validation,
>-		 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
>-		 */
> 		seq_printf(m, "DC3CO count: %d\n",
>-			   intel_de_read(i915, IS_DGFX(i915) ?
>-					 DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3));
>+			   intel_de_read(i915, dc3co_reg));
> 	} else {
> 		dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT :
> 			SKL_DMC_DC3_DC5_COUNT;
>-- 
>2.25.1
>