[Intel-gfx] [PATCH] drm/i915/pvc: Update forcewake domain for CCS register ranges

[Chegondi, Harish]

On Fri, 2022-10-14 at 16:30 -0700, Matt Roper wrote:
> The bspec was just updated with a correction to the forcewake domain
> required when accessing registers in the CCS engine ranges (0x1a000 -
> 0x1ffff and 0x26000 - 0x27fff) on PVC; these ranges require a wake on
> the RENDER domain, not the GT domain.
> 
> Bspec: 67609
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>

Reviewed-by: Harish Chegondi <harish.chegondi at intel.com>

>  drivers/gpu/drm/i915/intel_uncore.c | 22 ++++++++++++----------
>  1 file changed, 12 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index c058cdc6d8a0..2a3e2869fe71 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1682,25 +1682,27 @@ static const struct intel_forcewake_range
> __pvc_fw_ranges[] = {
>         GEN_FW_RANGE(0x12000, 0x12fff, 0), /*
>                 0x12000 - 0x127ff: always on
>                 0x12800 - 0x12fff: reserved */
> -       GEN_FW_RANGE(0x13000, 0x23fff, FORCEWAKE_GT), /*
> +       GEN_FW_RANGE(0x13000, 0x19fff, FORCEWAKE_GT), /*
>                 0x13000 - 0x135ff: gt
>                 0x13600 - 0x147ff: reserved
>                 0x14800 - 0x153ff: gt
> -               0x15400 - 0x19fff: reserved
> -               0x1a000 - 0x1ffff: gt
> -               0x20000 - 0x21fff: reserved
> -               0x22000 - 0x23fff: gt */
> +               0x15400 - 0x19fff: reserved */
> +       GEN_FW_RANGE(0x1a000, 0x21fff, FORCEWAKE_RENDER), /*
> +               0x1a000 - 0x1ffff: render
> +               0x20000 - 0x21fff: reserved */
> +       GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
>         GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
>                 24000 - 0x2407f: always on
>                 24080 - 0x2417f: reserved */
> -       GEN_FW_RANGE(0x24180, 0x3ffff, FORCEWAKE_GT), /*
> +       GEN_FW_RANGE(0x24180, 0x25fff, FORCEWAKE_GT), /*
>                 0x24180 - 0x241ff: gt
>                 0x24200 - 0x251ff: reserved
>                 0x25200 - 0x252ff: gt
> -               0x25300 - 0x25fff: reserved
> -               0x26000 - 0x27fff: gt
> -               0x28000 - 0x2ffff: reserved
> -               0x30000 - 0x3ffff: gt */
> +               0x25300 - 0x25fff: reserved */
> +       GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /*
> +               0x26000 - 0x27fff: render
> +               0x28000 - 0x2ffff: reserved */
> +       GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
>         GEN_FW_RANGE(0x40000, 0x1bffff, 0),
>         GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
>                 0x1c0000 - 0x1c2bff: VD0