[Intel-gfx] [PATCH 1/5] drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf

[Rodrigo Vivi]

On Wed, Oct 19, 2022 at 04:37:17PM -0700, Ashutosh Dixit wrote:
> Instead of masks/shifts settle on REG_FIELD_GET as the standard way to
> extract reg fields. This allows future patches touching this code to also
> consistently use REG_FIELD_GET and friends.
> 
> Suggested-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit at intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c |  2 +-
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h       | 12 ++++--------
>  drivers/gpu/drm/i915/gt/intel_rps.c           | 11 +++++------
>  3 files changed, 10 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 40d0a3be42acf..979e602946549 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -307,7 +307,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
>  		drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
>  			   MEMSTAT_VID_SHIFT);
>  		drm_printf(p, "Current P-state: %d\n",
> -			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
> +			   REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rgvstat));
>  	} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
>  		u32 rpmodectl, freq_sts;
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 36d95b79022c0..35c039573294c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -794,12 +794,9 @@
>  #define GEN6_RP_DOWN_TIMEOUT			_MMIO(0xa010)
>  #define GEN6_RP_INTERRUPT_LIMITS		_MMIO(0xa014)
>  #define GEN6_RPSTAT1				_MMIO(0xa01c)
> -#define   GEN6_CAGF_SHIFT			8
> -#define   HSW_CAGF_SHIFT			7
> -#define   GEN9_CAGF_SHIFT			23
> -#define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
> -#define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
> -#define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
> +#define   GEN6_CAGF_MASK			REG_GENMASK(14, 8)
> +#define   HSW_CAGF_MASK				REG_GENMASK(13, 7)
> +#define   GEN9_CAGF_MASK			REG_GENMASK(31, 23)
>  #define GEN6_RP_CONTROL				_MMIO(0xa024)
>  #define   GEN6_RP_MEDIA_TURBO			(1 << 11)
>  #define   GEN6_RP_MEDIA_MODE_MASK		(3 << 9)
> @@ -1370,8 +1367,7 @@
>  #define MEMSTAT_ILK				_MMIO(0x111f8)
>  #define   MEMSTAT_VID_MASK			0x7f00
>  #define   MEMSTAT_VID_SHIFT			8
> -#define   MEMSTAT_PSTATE_MASK			0x00f8
> -#define   MEMSTAT_PSTATE_SHIFT			3
> +#define   MEMSTAT_PSTATE_MASK			REG_GENMASK(7, 3)
>  #define   MEMSTAT_MON_ACTV			(1 << 2)
>  #define   MEMSTAT_SRC_CTL_MASK			0x0003
>  #define   MEMSTAT_SRC_CTL_CORE			0
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index fc23c562d9b2a..5bd6671554a6e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2074,16 +2074,15 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
>  	u32 cagf;
>  
>  	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> -		cagf = (rpstat >> 8) & 0xff;
> +		cagf = REG_FIELD_GET(RPE_MASK, rpstat);
>  	else if (GRAPHICS_VER(i915) >= 9)
> -		cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> +		cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat);
>  	else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> -		cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
> +		cagf = REG_FIELD_GET(HSW_CAGF_MASK, rpstat);
>  	else if (GRAPHICS_VER(i915) >= 6)
> -		cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
> +		cagf = REG_FIELD_GET(GEN6_CAGF_MASK, rpstat);
>  	else
> -		cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >>
> -					MEMSTAT_PSTATE_SHIFT);
> +		cagf = gen5_invert_freq(rps, REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rpstat));
>  
>  	return cagf;
>  }
> -- 
> 2.38.0
>