[Intel-gfx] [PATCH] drm/i915: do not reset PLANE_SURF on plane disable on older gens

[Ville Syrjälä]

On Mon, Sep 05, 2022 at 07:02:40PM +0200, Andrzej Hajda wrote:
> 
> 
> On 05.09.2022 13:48, Ville Syrjälä wrote:
> > On Mon, Sep 05, 2022 at 10:05:00AM +0200, Andrzej Hajda wrote:
> >> In case of ICL and older generations disabling plane and/or disabling
> >> async update is always performed on vblank,
> > It should only be broken on bdw-glk (see. need_async_flip_disable_wa).
> 
> On CFL it is reported every drmtip run:
> https://intel-gfx-ci.01.org/tree/drm-tip/drmtip.html?testfilter=tiled-max-hw
> https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1209/fi-cfl-8109u/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html#dmesg-warnings402
> https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1209/fi-cfl-8109u/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html#dmesg-warnings402
> https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1209/fi-cfl-8109u/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
> https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1208/fi-cfl-8109u/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
> ...
> On APL it is less frequent, probably due to other bugs preventing run of 
> this test, last seen at:
> https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1190/fi-apl-guc/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
> Similar for SKL:
> https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1181/fi-skl-guc/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
> 
> I am not sure if I correctly read the docs but [1] says that 9th bit of 
> PLANE_CFG (Async Address Update Enable) is "not double buffered and the 
> changes will apply immediately" only for ICL, JSL, LKF1.

It got broken in bdw and fixed again in icl.

> So the change is not necessary in case of icl_plane_disable_arm.
> 
> [1]: https://gfxspecs.intel.com/Predator/Home/Index/7656
> >
> >> but if async update is enabled
> >> PLANE_SURF register is updated asynchronously. Writing 0 to PLANE_SURF
> >> when plane is still enabled can cause DMAR/PIPE errors.
> >> On the other side PLANE_SURF is used to arm plane registers - we need to
> >> write to it to trigger update on VBLANK, writting current value should
> >> be safe - the buffer address is valid till vblank.
> > I think you're effectively saying that somehow the async
> > flip disable w/a is not kicking in sometimes.
> 
> I was not aware of existence of this w/a and I am little lost in 
> figuring out how this w/a can prevent zeroing PLANE_SURF too early.

When it works as designed it should:
1. turn off the async flip bit
2. wait for vblank so that gets latched
3. do the sync plane update/disable normally

-- 
Ville Syrjälä
Intel